From patchwork Thu Apr 17 06:55:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rishikesh Donadkar X-Patchwork-Id: 882514 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12CFB220685; Thu, 17 Apr 2025 06:56:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744873011; cv=none; b=lbc3AUktn7ui9sc/ltEn/8inq4ejRMpzNfyGnsqtdHst2xLwxUR88HDcI81ONdKcAXvGcSlAxVgdCWs2ztJYU51KEv4+pLypjSoO7+Y+KZhBxas4Eup/8X1EeSyjVq3wcxFUwGI6VO/WvZHfnN/WuW5r9IVfF8Pwse0/gy1r37A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744873011; c=relaxed/simple; bh=ROrqHy/1Qd7Up8lbGYzAed7xBW/Epiy8rq7wjiIPS7g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YfNpxZSrKbjp+U7juOd2D2h/lPW/QMj1Qd+l2rKVvkwB89CuYdCCR1g3uS3VyzDl3VLYlD2DOpfQkfbFaaJef5BAiktHYpNIv3rNrGN8srY1ODpQn3dfxP0rEDsFdSRW/+OomoaBg2un1V9gjZtLBtkFqnpMzkJtCB6N412NQNI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=nGdTZW0/; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="nGdTZW0/" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53H6ubkX584231 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 17 Apr 2025 01:56:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1744872997; bh=92zouDESxfYPwNSJfsCOtvuk3b1B30f5Pk5T3yNiWJg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nGdTZW0/Gwyp0JYYO60xkQ5pKe4aNasPgVhodjaUoyBOZ+N2EVSpeEZkc1MqbSm6V VMMKgFG3e5Mdbd8stxXYBwNXz63BuYfS6XmQG1PFYyOCjA2ZB7SaRWwja7GJPGYRNK N8tdZvNis2g4nrMc5A7UP9n0uCpwk3kiqTAvqyBM= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53H6ubWO100179 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 17 Apr 2025 01:56:37 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 17 Apr 2025 01:56:36 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 17 Apr 2025 01:56:36 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [10.24.69.232]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53H6tsx6035403; Thu, 17 Apr 2025 01:56:30 -0500 From: Rishikesh Donadkar To: , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 06/13] media: ti: j721e-csi2rx: get number of contexts from device tree Date: Thu, 17 Apr 2025 12:25:47 +0530 Message-ID: <20250417065554.437541-7-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250417065554.437541-1-r-donadkar@ti.com> References: <20250417065554.437541-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea From: Pratyush Yadav Different platforms that use this driver might have different number of DMA channels allocated for CSI. So only as many DMA contexts can be used as the number of DMA channels available. Get the number of channels provided via device tree and only configure that many contexts, and hence only that many pads. Signed-off-by: Pratyush Yadav Co-developed-by: Jai Luthra Signed-off-by: Jai Luthra Signed-off-by: Rishikesh Donadkar --- .../platform/ti/j721e-csi2rx/j721e-csi2rx.c | 41 ++++++++++++++----- 1 file changed, 30 insertions(+), 11 deletions(-) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index ea7e331e872af..e85d04d7c2ff9 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -40,7 +40,7 @@ #define SHIM_PSI_CFG0_DST_TAG GENMASK(31, 16) #define PSIL_WORD_SIZE_BYTES 16 -#define TI_CSI2RX_NUM_CTX 1 +#define TI_CSI2RX_MAX_CTX 32 /* * There are no hard limits on the width or height. The DMA engine can handle @@ -53,8 +53,8 @@ #define TI_CSI2RX_PAD_SINK 0 #define TI_CSI2RX_PAD_FIRST_SOURCE 1 -#define TI_CSI2RX_NUM_SOURCE_PADS 1 -#define TI_CSI2RX_NUM_PADS (1 + TI_CSI2RX_NUM_SOURCE_PADS) +#define TI_CSI2RX_MAX_SOURCE_PADS TI_CSI2RX_MAX_CTX +#define TI_CSI2RX_MAX_PADS (1 + TI_CSI2RX_MAX_SOURCE_PADS) #define DRAIN_TIMEOUT_MS 50 #define DRAIN_BUFFER_SIZE SZ_32K @@ -112,14 +112,15 @@ struct ti_csi2rx_dev { void __iomem *shim; struct mutex mutex; /* To serialize ioctls. */ unsigned int enable_count; + unsigned int num_ctx; struct v4l2_device v4l2_dev; struct media_device mdev; struct media_pipeline pipe; - struct media_pad pads[TI_CSI2RX_NUM_PADS]; + struct media_pad pads[TI_CSI2RX_MAX_PADS]; struct v4l2_async_notifier notifier; struct v4l2_subdev *source; struct v4l2_subdev subdev; - struct ti_csi2rx_ctx ctx[TI_CSI2RX_NUM_CTX]; + struct ti_csi2rx_ctx ctx[TI_CSI2RX_MAX_CTX]; /* Buffer to drain stale data from PSI-L endpoint */ struct { void *vaddr; @@ -449,7 +450,7 @@ static int csi_async_notifier_complete(struct v4l2_async_notifier *notifier) return ret; /* Create and link video nodes for all DMA contexts */ - for (i = 0; i < TI_CSI2RX_NUM_CTX; i++) { + for (i = 0; i < csi->num_ctx; i++) { struct ti_csi2rx_ctx *ctx = &csi->ctx[i]; struct video_device *vdev = &ctx->vdev; @@ -1212,10 +1213,11 @@ static int ti_csi2rx_v4l2_init(struct ti_csi2rx_dev *csi) csi->pads[TI_CSI2RX_PAD_SINK].flags = MEDIA_PAD_FL_SINK; for (unsigned int i = TI_CSI2RX_PAD_FIRST_SOURCE; - i < TI_CSI2RX_NUM_PADS; i++) + i < TI_CSI2RX_PAD_FIRST_SOURCE + csi->num_ctx; i++) csi->pads[i].flags = MEDIA_PAD_FL_SOURCE; - ret = media_entity_pads_init(&sd->entity, ARRAY_SIZE(csi->pads), + ret = media_entity_pads_init(&sd->entity, + TI_CSI2RX_PAD_FIRST_SOURCE + csi->num_ctx, csi->pads); if (ret) goto unregister_media; @@ -1301,8 +1303,9 @@ static int ti_csi2rx_init_ctx(struct ti_csi2rx_ctx *ctx) static int ti_csi2rx_probe(struct platform_device *pdev) { + struct device_node *np = pdev->dev.of_node; struct ti_csi2rx_dev *csi; - int ret, i; + int ret, i, count; csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL); if (!csi) @@ -1324,13 +1327,29 @@ static int ti_csi2rx_probe(struct platform_device *pdev) if (!csi->drain.vaddr) return -ENOMEM; + /* Only use as many contexts as the number of DMA channels allocated. */ + count = of_property_count_strings(np, "dma-names"); + if (count < 0) { + dev_err(csi->dev, "Failed to get DMA channel count: %d\n", + count); + return count; + } + + csi->num_ctx = count; + if (csi->num_ctx > TI_CSI2RX_MAX_CTX) { + dev_warn(csi->dev, + "%u DMA channels passed. Maximum is %u. Ignoring the rest.\n", + csi->num_ctx, TI_CSI2RX_MAX_CTX); + csi->num_ctx = TI_CSI2RX_MAX_CTX; + } + mutex_init(&csi->mutex); ret = ti_csi2rx_v4l2_init(csi); if (ret) goto err_v4l2; - for (i = 0; i < TI_CSI2RX_NUM_CTX; i++) { + for (i = 0; i < csi->num_ctx; i++) { csi->ctx[i].idx = i; csi->ctx[i].csi = csi; ret = ti_csi2rx_init_ctx(&csi->ctx[i]); @@ -1369,7 +1388,7 @@ static void ti_csi2rx_remove(struct platform_device *pdev) struct ti_csi2rx_dev *csi = platform_get_drvdata(pdev); unsigned int i; - for (i = 0; i < TI_CSI2RX_NUM_CTX; i++) + for (i = 0; i < csi->num_ctx; i++) ti_csi2rx_cleanup_ctx(&csi->ctx[i]); ti_csi2rx_cleanup_notifier(csi);