diff mbox series

[19/20] clk: sp7021: switch to HWORD_UPDATE macro

Message ID 20250612-byeword-update-v1-19-f4afb8f6313f@collabora.com
State New
Headers show
Series BYEWORD_UPDATE: unifying (most) HIWORD_UPDATE macros | expand

Commit Message

Nicolas Frattaroli June 12, 2025, 6:56 p.m. UTC 
The sp7021 clock driver has its own shifted high word mask macro,
similar to the ones many Rockchip drivers have.

Remove it, and replace instances of it with bitfield.h's HWORD_UPDATE
macro, which does the same thing except in a common macro that also does
compile-time error checking.

This was compile-tested with 32-bit ARM with Clang, no runtime tests
were performed as I lack the hardware. However, I verified that fix
commit 5c667d5a5a3e ("clk: sp7021: Adjust width of _m in HWM_FIELD_PREP()")
is not regressed. No warning is produced.

Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
 drivers/clk/clk-sp7021.c | 21 +++++++--------------
 1 file changed, 7 insertions(+), 14 deletions(-)
diff mbox series

Patch

diff --git a/drivers/clk/clk-sp7021.c b/drivers/clk/clk-sp7021.c
index 7cb7d501d7a6ebffe002f80dfa937365e04d356a..f408109f866c6ee65398d549e76994e54c1421ea 100644
--- a/drivers/clk/clk-sp7021.c
+++ b/drivers/clk/clk-sp7021.c
@@ -38,13 +38,6 @@  enum {
 #define MASK_DIVN	GENMASK(7, 0)
 #define MASK_DIVM	GENMASK(14, 8)
 
-/* HIWORD_MASK FIELD_PREP */
-#define HWM_FIELD_PREP(mask, value)		\
-({						\
-	u64 _m = mask;				\
-	(_m << 16) | FIELD_PREP(_m, value);	\
-})
-
 struct sp_pll {
 	struct clk_hw hw;
 	void __iomem *reg;
@@ -313,15 +306,15 @@  static int plltv_set_rate(struct sp_pll *clk)
 	u32 r0, r1, r2;
 
 	r0  = BIT(clk->bp_bit + 16);
-	r0 |= HWM_FIELD_PREP(MASK_SEL_FRA, clk->p[SEL_FRA]);
-	r0 |= HWM_FIELD_PREP(MASK_SDM_MOD, clk->p[SDM_MOD]);
-	r0 |= HWM_FIELD_PREP(MASK_PH_SEL, clk->p[PH_SEL]);
-	r0 |= HWM_FIELD_PREP(MASK_NFRA, clk->p[NFRA]);
+	r0 |= HWORD_UPDATE(MASK_SEL_FRA, clk->p[SEL_FRA]);
+	r0 |= HWORD_UPDATE(MASK_SDM_MOD, clk->p[SDM_MOD]);
+	r0 |= HWORD_UPDATE(MASK_PH_SEL, clk->p[PH_SEL]);
+	r0 |= HWORD_UPDATE(MASK_NFRA, clk->p[NFRA]);
 
-	r1  = HWM_FIELD_PREP(MASK_DIVR, clk->p[DIVR]);
+	r1  = HWORD_UPDATE(MASK_DIVR, clk->p[DIVR]);
 
-	r2  = HWM_FIELD_PREP(MASK_DIVN, clk->p[DIVN] - 1);
-	r2 |= HWM_FIELD_PREP(MASK_DIVM, clk->p[DIVM] - 1);
+	r2  = HWORD_UPDATE(MASK_DIVN, clk->p[DIVN] - 1);
+	r2 |= HWORD_UPDATE(MASK_DIVM, clk->p[DIVM] - 1);
 
 	spin_lock_irqsave(&clk->lock, flags);
 	writel(r0, clk->reg);