From patchwork Thu May 23 17:07:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Capper X-Patchwork-Id: 17165 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-gh0-f198.google.com (mail-gh0-f198.google.com [209.85.160.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 0DBC72395B for ; Thu, 23 May 2013 17:09:48 +0000 (UTC) Received: by mail-gh0-f198.google.com with SMTP id r13sf3940319ghr.5 for ; Thu, 23 May 2013 10:08:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-beenthere:x-forwarded-to:x-forwarded-for :delivered-to:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=bwofLpLUUZo3inGc+bFNOV5T6cqcDF0JSYQ55AZOGuI=; b=CEAcwnTnIJsVHwDM6vHA9C2NXE5mGRcsDRwKetipa/YAmYC3DaU1UypmNoLvSqTyaU pX4g8WjY14V2MiMw1fbiKb+hakTR2IwQ76prHz5NDkFKuWiQ/WaBi07xcN9zM+FkSmab Ng/g3isVqlYIiegm2VMhPvfKFY95DTLUXBEYgQav9gMdB3Q9U1n7lxFSjr/HhtpW2pQe nC02gQTgF3t1QPBAO24+kciwjOf1u9gCc6zQVR9IJOAjd7hGzAG57xG0uYczG+aiBt3/ oO2FbqZ8UzPRMUE+o1KhMnXWSqxupwj1PvF7gfug3d686ZoGYTS642OCeTPD46FruLG6 C18Q== X-Received: by 10.236.68.164 with SMTP id l24mr6680896yhd.19.1369328932577; Thu, 23 May 2013 10:08:52 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.97.4 with SMTP id dw4ls1508060qeb.58.gmail; Thu, 23 May 2013 10:08:52 -0700 (PDT) X-Received: by 10.52.249.41 with SMTP id yr9mr5209277vdc.17.1369328932316; Thu, 23 May 2013 10:08:52 -0700 (PDT) Received: from mail-vb0-x230.google.com (mail-vb0-x230.google.com [2607:f8b0:400c:c02::230]) by mx.google.com with ESMTPS id tn5si6880436vdc.91.2013.05.23.10.08.52 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 23 May 2013 10:08:52 -0700 (PDT) Received-SPF: neutral (google.com: 2607:f8b0:400c:c02::230 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=2607:f8b0:400c:c02::230; Received: by mail-vb0-f48.google.com with SMTP id w8so1435628vbf.21 for ; Thu, 23 May 2013 10:08:52 -0700 (PDT) X-Received: by 10.52.163.207 with SMTP id yk15mr5023120vdb.42.1369328932025; Thu, 23 May 2013 10:08:52 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.126.138 with SMTP id c10csp61560vcs; Thu, 23 May 2013 10:08:51 -0700 (PDT) X-Received: by 10.180.185.179 with SMTP id fd19mr26434747wic.1.1369328908890; Thu, 23 May 2013 10:08:28 -0700 (PDT) Received: from mail-we0-x231.google.com (mail-we0-x231.google.com [2a00:1450:400c:c03::231]) by mx.google.com with ESMTPS id y16si9587023wij.40.2013.05.23.10.08.28 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 23 May 2013 10:08:28 -0700 (PDT) Received-SPF: neutral (google.com: 2a00:1450:400c:c03::231 is neither permitted nor denied by best guess record for domain of steve.capper@linaro.org) client-ip=2a00:1450:400c:c03::231; Received: by mail-we0-f177.google.com with SMTP id n57so2165750wev.36 for ; Thu, 23 May 2013 10:08:28 -0700 (PDT) X-Received: by 10.180.86.38 with SMTP id m6mr45379765wiz.25.1369328902254; Thu, 23 May 2013 10:08:22 -0700 (PDT) Received: from localhost.localdomain (marmot.wormnet.eu. [188.246.204.87]) by mx.google.com with ESMTPSA id ca19sm36989435wib.3.2013.05.23.10.08.21 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 23 May 2013 10:08:21 -0700 (PDT) From: Steve Capper To: linux-mm@kvack.org, x86@kernel.org, linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michal Hocko , Ken Chen , Mel Gorman , Catalin Marinas , Will Deacon , patches@linaro.org, Steve Capper Subject: [PATCH 08/11] ARM64: mm: Swap PTE_FILE and PTE_PROT_NONE bits. Date: Thu, 23 May 2013 18:07:55 +0100 Message-Id: <1369328878-11706-9-git-send-email-steve.capper@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1369328878-11706-1-git-send-email-steve.capper@linaro.org> References: <1369328878-11706-1-git-send-email-steve.capper@linaro.org> X-Gm-Message-State: ALoCoQm+iYo3AxxqBGd+8sJvwOwi/CcFWCgZ2lIM3pgC6Pz5VqJLReOeYdNg9UqKmC+8zQEq21wj X-Original-Sender: steve.capper@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c02::230 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Under ARM64, PTEs can be broadly categorised as follows: - Present and valid: Bit #0 is set. The PTE is valid and memory access to the region may fault. - Present and invalid: Bit #0 is clear and bit #1 is set. Represents present memory with PROT_NONE protection. The PTE is an invalid entry, and the user fault handler will raise a SIGSEGV. - Not present (file): Bits #0 and #1 are clear, bit #2 is set. Memory represented has been paged out. The PTE is an invalid entry, and the fault handler will try and re-populate the memory where necessary. Huge PTEs are block descriptors that have bit #1 clear. If we wish to represent PROT_NONE huge PTEs we then run into a problem as there is no way to distinguish between regular and huge PTEs if we set bit #1. As huge PTEs are always present, the meaning of bits #1 and #2 can be swapped for invalid PTEs. This patch swaps the PTE_FILE and PTE_PROT_NONE constants, allowing us to represent PROT_NONE huge PTEs. Signed-off-by: Steve Capper Acked-by: Catalin Marinas --- arch/arm64/include/asm/pgtable.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 77b09d6..8867282 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -25,8 +25,8 @@ * Software defined PTE bits definition. */ #define PTE_VALID (_AT(pteval_t, 1) << 0) -#define PTE_PROT_NONE (_AT(pteval_t, 1) << 1) /* only when !PTE_VALID */ -#define PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !pte_present() */ +#define PTE_FILE (_AT(pteval_t, 1) << 1) /* only when !pte_present() */ +#define PTE_PROT_NONE (_AT(pteval_t, 1) << 2) /* only when !PTE_VALID */ #define PTE_DIRTY (_AT(pteval_t, 1) << 55) #define PTE_SPECIAL (_AT(pteval_t, 1) << 56) @@ -281,8 +281,8 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; /* * Encode and decode a swap entry: - * bits 0-1: present (must be zero) - * bit 2: PTE_FILE + * bits 0, 2: present (must both be zero) + * bit 1: PTE_FILE * bits 3-8: swap type * bits 9-63: swap offset */ @@ -306,8 +306,8 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; /* * Encode and decode a file entry: - * bits 0-1: present (must be zero) - * bit 2: PTE_FILE + * bits 0, 2: present (must both be zero) + * bit 1: PTE_FILE * bits 3-63: file offset / PAGE_SIZE */ #define pte_file(pte) (pte_val(pte) & PTE_FILE)