From patchwork Fri Nov 4 09:58:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mengqi Zhang X-Patchwork-Id: 621632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBC92C4332F for ; Fri, 4 Nov 2022 09:59:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229485AbiKDJ7Z (ORCPT ); Fri, 4 Nov 2022 05:59:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230051AbiKDJ7Y (ORCPT ); Fri, 4 Nov 2022 05:59:24 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 364861B785; Fri, 4 Nov 2022 02:59:23 -0700 (PDT) X-UUID: deebe08b21d04ee19bba5f35ec79e7b0-20221104 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=vWDvI9g2pRQ52ZMOm1a7Y9bqu87BMMp4jVyuY1u4zSw=; b=ZUeitW7vqeGmgAupTh+nOPEdmPpLTUpgELlA/Fy6C8n0Ya+R7enRBer7+JvWPgEi0fvPzvgw7Nf1P6FByc0g1IR2Bk4EtZ53Kzmz1qoz70tDQYQOiERWUSVsM0h5MXCzd37eNvtc9s9QXMjJTCoNH2OEFrUgqi3eLyRm3wInZxI=; X-CID-CACHE: Type:Local,Time:202211041751+08,HitQuantity:1 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12, REQID:30482c84-d367-40c6-a20c-7a6864a6b80f, IP:0, U RL:0,TC:0,Content:0,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-30 X-CID-META: VersionHash:62cd327, CLOUDID:f6a0aef3-a19e-4b45-8bfe-6a73c93611e9, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: deebe08b21d04ee19bba5f35ec79e7b0-20221104 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 603419516; Fri, 04 Nov 2022 17:59:15 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 4 Nov 2022 17:59:14 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 4 Nov 2022 17:59:13 +0800 From: Mengqi Zhang To: , , , , , , CC: , , , , Subject: [PATCH v2 0/2] Mediatek eMMC Inline Crypto Engine support Date: Fri, 4 Nov 2022 17:58:46 +0800 Message-ID: <20221104095848.27444-1-mengqi.zhang@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Change in v2 - change patch 1 commit title - change patch 2 commit title, and correct commit message - add crypto clock description base on new code base Mediatek eMMC hardware IP has Inline Crypto Engine (ICE), we support inline encryption now. This patchset supports Mediatek eMMC inline encryption which meets the upcoming version of the eMMC specification such as v5.1 or v5.2. Patch 1, add crypto clock control flow in mtk-sd driver, patch 2, document the device tree description about crypto clock. Mengqi Zhang (2): mmc: mtk-sd: add Inline Crypto Engine clock control dt-bindings: mmc: mtk-sd: add Inline Crypto Engine clock .../devicetree/bindings/mmc/mtk-sd.yaml | 22 +++++++++++++++++++ drivers/mmc/host/mtk-sd.c | 12 ++++++++++ 2 files changed, 34 insertions(+) --- 2.25.1