Message ID | 20241023092708.604195-1-quic_yuanjiey@quicinc.com |
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Wed, 23 Oct 2024 09:28:05 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 49N9S3tF016260; Wed, 23 Oct 2024 09:28:03 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 42cpckqq25-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 23 Oct 2024 09:28:03 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 49N9S3Bb016238; Wed, 23 Oct 2024 09:28:03 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (cse-cd02-lnx.qualcomm.com [10.64.75.246]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 49N9S2Cx016230 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 23 Oct 2024 09:28:03 +0000 Received: by cse-cd02-lnx.ap.qualcomm.com (Postfix, from userid 4571896) id 7A7E6137B; Wed, 23 Oct 2024 17:28:01 +0800 (CST) From: Yuanjie Yang <quic_yuanjiey@quicinc.com> To: ulf.hansson@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, bhupesh.sharma@linaro.org, andersson@kernel.org, konradybcio@kernel.org Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_tingweiz@quicinc.com, Yuanjie Yang <quic_yuanjiey@quicinc.com> Subject: [PATCH v1 0/3] Enable emmc and SD on QCS615 Date: Wed, 23 Oct 2024 17:27:05 +0800 Message-Id: <20241023092708.604195-1-quic_yuanjiey@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: <linux-mmc.vger.kernel.org> List-Subscribe: <mailto:linux-mmc+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-mmc+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: T-tugc3eDUQJyZEF7YWgYe-RzSegNURI X-Proofpoint-GUID: T-tugc3eDUQJyZEF7YWgYe-RzSegNURI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 impostorscore=0 spamscore=0 phishscore=0 mlxlogscore=991 lowpriorityscore=0 clxscore=1011 malwarescore=0 bulkscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410230058 |
Series | Enable emmc and SD on QCS615 | expand |
Add SD and emmc support to the QCS615 Ride platform. The SD controller and emmc controller of QCS615 are derived from SM6115. Include the relevant binding documents accordingly. Additionally, configure emmc-related and SD-related opp, power, and interconnect settings in the device tree. Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com> --- This patch series depends on below patch series: https://lore.kernel.org/all/20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com/ https://lore.kernel.org/all/20241011063112.19087-1-quic_qqzhou@quicinc.com/ Yuanjie Yang (3): dt-bindings: mmc: Add sdhci compatible for QCS615 arm64: dts: qcom: qcs615: add SD and emmc node arm64: dts: qcom: qcs615-ride: Enable SD and emmc node .../devicetree/bindings/mmc/sdhci-msm.yaml | 1 + arch/arm64/boot/dts/qcom/qcs615-ride.dts | 31 +++ arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 ++++++++++++++++++ 3 files changed, 230 insertions(+)