From patchwork Wed Jan 9 16:17:02 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 13949 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 08A3823E21 for ; Wed, 9 Jan 2013 16:17:48 +0000 (UTC) Received: from mail-vc0-f180.google.com (mail-vc0-f180.google.com [209.85.220.180]) by fiordland.canonical.com (Postfix) with ESMTP id 969DCA190ED for ; Wed, 9 Jan 2013 16:17:47 +0000 (UTC) Received: by mail-vc0-f180.google.com with SMTP id p16so1699670vcq.39 for ; Wed, 09 Jan 2013 08:17:47 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:from:to:cc:subject:date:message-id:x-mailer :mime-version:content-type:x-gm-message-state; bh=jA6wH+LbFtjbCNo5VR1HpkrJ46SW1Usvcc+FUOpG8FU=; b=eEH0Zq/CVo9/g14X53bCRP2zlLFaGnrg8O9JcfDBAFQeRY4LWQjPgEPmKS7WF9opE2 BpjwLJegBUap10VCtcJkk5NORbJkmXzQjqk1Rt0MvYUDgZYN1tkQG/+1eQ+gPi6UUSz1 dlF1Gw5d2PfVb2dAeF040GDC2kdoJbqV1iQJKXv4rWAUx6UfxA5yoN5r1luctv/IKT6G 95yPOnrPnBPaMNMHgkcgxPj0gZYTNbAjPTggWJ+MhrWn1cla7DwCJ4vleJ78p5B253IW 1H0WBYXCjzfEwAsM0+fwRCI+OuQhMxCX1TQafh0/L9GPcJMNSKBGZzek99z43way3tt2 fvCA== X-Received: by 10.52.18.207 with SMTP id y15mr77203837vdd.8.1357748267015; Wed, 09 Jan 2013 08:17:47 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.145.101 with SMTP id st5csp23234veb; Wed, 9 Jan 2013 08:17:40 -0800 (PST) X-Received: by 10.180.80.170 with SMTP id s10mr3779528wix.27.1357748260043; Wed, 09 Jan 2013 08:17:40 -0800 (PST) Received: from eu1sys200aog120.obsmtp.com (eu1sys200aog120.obsmtp.com [207.126.144.149]) by mx.google.com with SMTP id 47si30405111eea.99.2013.01.09.08.17.33 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 09 Jan 2013 08:17:40 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.149 is neither permitted nor denied by best guess record for domain of ulf.hansson@stericsson.com) client-ip=207.126.144.149; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.149 is neither permitted nor denied by best guess record for domain of ulf.hansson@stericsson.com) smtp.mail=ulf.hansson@stericsson.com Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob120.postini.com ([207.126.147.11]) with SMTP ID DSNKUO2YGGDcI+0F7V16stz5j7PsbZbsUaqY@postini.com; Wed, 09 Jan 2013 16:17:39 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id C46CB3B; Wed, 9 Jan 2013 16:16:27 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id 4628C59; Wed, 9 Jan 2013 10:45:19 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id F28F3A807E; Wed, 9 Jan 2013 17:17:02 +0100 (CET) Received: from steludxu1397.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 9 Jan 2013 17:17:08 +0100 From: Ulf Hansson To: , Chris Ball Cc: , Russell King , Linus Walleij , Johan Rudholm , Ulf Hansson Subject: [PATCH V2] mmc: mmci: Fixup clock gating when freq is 0 for ST-variants Date: Wed, 9 Jan 2013 17:17:02 +0100 Message-ID: <1357748222-26829-1-git-send-email-ulf.hansson@stericsson.com> X-Mailer: git-send-email 1.7.10 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQnQEwcclhWVIt+ZMEEko9zqesFQEVhcXTUhHrkH0dcTJQDM6NkvpIDQq4BnVyu4ewxoMwp+ From: Johan Rudholm In the ST Micro variant, the MMCICLOCK register must not be used to gate the clock. Instead use MMCIPOWER register and by clearing the PWR_ON bit to do this. Signed-off-by: Johan Rudholm Signed-off-by: Ulf Hansson --- Changes in v2: Both the nomadik and u300 variants uses the MMCIPOWER register to gate the clock. Enable this for those variants as well. --- drivers/mmc/host/mmci.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 1507723..5272e97 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -59,6 +59,7 @@ static unsigned int fmax = 515633; * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register * @pwrreg_powerup: power up value for MMCIPOWER register * @signal_direction: input/out direction of bus signals can be indicated + * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock */ struct variant_data { unsigned int clkreg; @@ -71,6 +72,7 @@ struct variant_data { bool blksz_datactrl16; u32 pwrreg_powerup; bool signal_direction; + bool pwrreg_clkgate; }; static struct variant_data variant_arm = { @@ -95,6 +97,7 @@ static struct variant_data variant_u300 = { .sdio = true, .pwrreg_powerup = MCI_PWR_ON, .signal_direction = true, + .pwrreg_clkgate = true, }; static struct variant_data variant_nomadik = { @@ -106,6 +109,7 @@ static struct variant_data variant_nomadik = { .st_clkdiv = true, .pwrreg_powerup = MCI_PWR_ON, .signal_direction = true, + .pwrreg_clkgate = true, }; static struct variant_data variant_ux500 = { @@ -118,6 +122,7 @@ static struct variant_data variant_ux500 = { .st_clkdiv = true, .pwrreg_powerup = MCI_PWR_ON, .signal_direction = true, + .pwrreg_clkgate = true, }; static struct variant_data variant_ux500v2 = { @@ -131,6 +136,7 @@ static struct variant_data variant_ux500v2 = { .blksz_datactrl16 = true, .pwrreg_powerup = MCI_PWR_ON, .signal_direction = true, + .pwrreg_clkgate = true, }; /* @@ -1154,6 +1160,13 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) } } + /* + * If clock = 0 and the variant requires the MMCIPOWER to be used for + * gating the clock, the MCI_PWR_ON bit is cleared. + */ + if (!ios->clock && variant->pwrreg_clkgate) + pwr &= ~MCI_PWR_ON; + spin_lock_irqsave(&host->lock, flags); mmci_set_clkreg(host, ios->clock);