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[209.132.180.67]) by mx.google.com with ESMTP id c5si4851076pdf.249.2015.09.04.08.35.03; Fri, 04 Sep 2015 08:35:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932848AbbIDPe5 (ORCPT + 28 others); Fri, 4 Sep 2015 11:34:57 -0400 Received: from mail-pa0-f46.google.com ([209.85.220.46]:36502 "EHLO mail-pa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932700AbbIDPey (ORCPT ); Fri, 4 Sep 2015 11:34:54 -0400 Received: by pacwi10 with SMTP id wi10so27515093pac.3 for ; Fri, 04 Sep 2015 08:34:54 -0700 (PDT) X-Received: by 10.68.241.103 with SMTP id wh7mr9493871pbc.88.1441380894121; Fri, 04 Sep 2015 08:34:54 -0700 (PDT) Received: from localhost.localdomain ([202.62.93.137]) by smtp.gmail.com with ESMTPSA id gs2sm2920151pbc.15.2015.09.04.08.34.50 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 04 Sep 2015 08:34:53 -0700 (PDT) From: Vaibhav Hiremath To: linux-mmc@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kliu5@marvell.com, ulf.hansson@linaro.org, Vaibhav Hiremath Subject: [PATCH 3/5] mmc: sdhci-pxav3: Add pinctl setting according to bus clock Date: Fri, 4 Sep 2015 21:02:19 +0530 Message-Id: <1441380741-13115-4-git-send-email-vaibhav.hiremath@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1441380741-13115-1-git-send-email-vaibhav.hiremath@linaro.org> References: <1441380741-13115-1-git-send-email-vaibhav.hiremath@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: vaibhav.hiremath@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.49 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Different bus clock may need different pin setting. For example, fast bus clock like 208Mhz need pin drive fast while slow bus clock prefer pin drive slow to guarantee signal quality. So this patch creates two states, - Default (slow/normal) pin state - And fast pin state for higher freq bus speed. And selection of pin state is done based on timing mode. Signed-off-by: Vaibhav Hiremath Signed-off-by: Kevin Liu --- drivers/mmc/host/sdhci-pxav3.c | 45 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index c2b2b78..d933f75 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "sdhci.h" #include "sdhci-pltfm.h" @@ -92,6 +93,10 @@ struct sdhci_pxa { void __iomem *io_pwr_reg; void __iomem *io_pwr_lock_reg; struct sdhci_pxa_data *data; + + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_fast; }; static struct sdhci_pxa_data pxav3_data_v1 = { @@ -298,6 +303,33 @@ static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode) pxa->power_mode = power_mode; } +static int pxav3_select_pinstate(struct sdhci_host *host, unsigned int uhs) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_pxa *pxa = pltfm_host->priv; + struct pinctrl_state *pinctrl; + + if (IS_ERR(pxa->pinctrl) || + IS_ERR(pxa->pins_default) || + IS_ERR(pxa->pins_fast)) + return -EINVAL; + + switch (uhs) { + case MMC_TIMING_UHS_SDR50: + case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_MMC_HS200: + case MMC_TIMING_MMC_HS400: + pinctrl = pxa->pins_fast; + break; + default: + /* back to default state for other legacy timing */ + pinctrl = pxa->pins_default; + break; + } + + return pinctrl_select_state(pxa->pinctrl, pinctrl); +} + static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -353,6 +385,8 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) dev_dbg(mmc_dev(host->mmc), "%s uhs = %d, ctrl_2 = %04X\n", __func__, uhs, ctrl_2); + + pxav3_select_pinstate(host, uhs); } static void pxav3_voltage_switch(struct sdhci_host *host, @@ -416,7 +450,6 @@ static void pxav3_set_clock(struct sdhci_host *host, unsigned int clock) /* TX internal clock selection */ pxav3_set_tx_clock(host); } - } static const struct sdhci_ops pxav3_sdhci_ops = { @@ -586,6 +619,16 @@ static int sdhci_pxav3_probe(struct platform_device *pdev) } } + pxa->pinctrl = devm_pinctrl_get(dev); + if (!IS_ERR(pxa->pinctrl)) { + pxa->pins_default = pinctrl_lookup_state(pxa->pinctrl, "default"); + if (IS_ERR(pxa->pins_default)) + dev_err(dev, "could not get default pinstate\n"); + pxa->pins_fast = pinctrl_lookup_state(pxa->pinctrl, "fast"); + if (IS_ERR(pxa->pins_fast)) + dev_info(dev, "could not get fast pinstate\n"); + } + pm_runtime_get_noresume(&pdev->dev); pm_runtime_set_active(&pdev->dev); pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);