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[209.132.180.67]) by mx.google.com with ESMTP id 33si168406plk.159.2017.06.14.01.25.41; Wed, 14 Jun 2017 01:25:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.b=Xo37D3y3; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754729AbdFNIZh (ORCPT + 6 others); Wed, 14 Jun 2017 04:25:37 -0400 Received: from mail-pf0-f178.google.com ([209.85.192.178]:35084 "EHLO mail-pf0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754730AbdFNIZd (ORCPT ); Wed, 14 Jun 2017 04:25:33 -0400 Received: by mail-pf0-f178.google.com with SMTP id l89so80812199pfi.2 for ; Wed, 14 Jun 2017 01:25:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=f3mJCACG6yYK13E6+M4zDZyak0D9DZxDEAeJvXkUGZQ=; b=Xo37D3y3ZxGY32KuuYNuqj6U00FrpemF0pko3lhRqq2Ypt1VPJx6lUChgNcpmFD0jc xjGFx7Kq+VgWTum3nCIDycQs10ELBZ7Dds2+RtVmqKbojjMWN56qqUhV6dzZ+7LO+Qig uUBk8CVSE7R/iG+Z3jBxqy/AcWsKK4E24Jhmc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=f3mJCACG6yYK13E6+M4zDZyak0D9DZxDEAeJvXkUGZQ=; b=tSa9kUUiyTqZg9ImoKM8YV32M2KzN6QoW305GNKf7dSxkkKmp2eJUEEJ8O5HM3f0ll SlgLzwb+peXliv7E6cXsahA8i2agJq4NmNNN0UGl1iR3cJ4Hphv/BCdKgkGpiqB3M3S5 rZTdO66nyk8FVANXEbaPQeT0NHDNXM32f9s4ppWL/LavFY/vGXARt4ZDVa1wGtBy7Mnl ylqWjIai0CRBZ8o7dD4tERb7NIIUWP/HFdwuLaglqKu2blqDepmTh9mR6QZRbukwvSXY siyk/aQAkHRIo/cxnSo6B7BWpLruxXdVGeHBtk/W/AxCCdJgeVa+vzQ1q/TRMoLvsWaO PYGg== X-Gm-Message-State: AKS2vOzMJjWOsLUYbZ+AwBwt4CbEpNpAWQqfhcS5MPHcSDmzz0nwTgaY O+ivW7nG4MS50vzy X-Received: by 10.84.129.36 with SMTP id 33mr3757054plb.94.1497428732468; Wed, 14 Jun 2017 01:25:32 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.99]) by smtp.gmail.com with ESMTPSA id h14sm766802pfh.71.2017.06.14.01.25.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 01:25:31 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com, lee.jones@linaro.org, ulf.hansson@linaro.org, bhelgaas@google.com, arnd@arndb.de Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-pci@vger.kernel.org, Xiaowei Song , Guodong Xu Subject: [PATCH v3 16/21] arm64: dts: hisi: add kirin pcie node Date: Wed, 14 Jun 2017 16:23:33 +0800 Message-Id: <20170614082338.15673-17-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170614082338.15673-1-guodong.xu@linaro.org> References: <20170614082338.15673-1-guodong.xu@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Xiaowei Song Add PCIe node for hi3660, and add binding documentation. Cc: Guodong Xu Signed-off-by: Xiaowei Song Acked-by: Arnd Bergmann --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 32 +++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 4101bf5..bdfdf27 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -817,5 +817,37 @@ cs-gpios = <&gpio18 5 0>; status = "disabled"; }; + + pcie@f4000000 { + compatible = "hisilicon,kirin960-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, + <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 + 0xf6000000 0x0 0x2000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, + <0x0 0 0 2 &gic 0 0 0 283 4>, + <0x0 0 0 3 &gic 0 0 0 284 4>, + <0x0 0 0 4 &gic 0 0 0 285 4>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + status = "ok"; + }; }; };