From patchwork Thu May 6 10:03:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steven Lee X-Patchwork-Id: 431933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EDE2C433B4 for ; Thu, 6 May 2021 10:06:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D2B5C61157 for ; Thu, 6 May 2021 10:06:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233832AbhEFKHR (ORCPT ); Thu, 6 May 2021 06:07:17 -0400 Received: from twspam01.aspeedtech.com ([211.20.114.71]:30090 "EHLO twspam01.aspeedtech.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234341AbhEFKHR (ORCPT ); Thu, 6 May 2021 06:07:17 -0400 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 1469pSEe024643; Thu, 6 May 2021 17:51:28 +0800 (GMT-8) (envelope-from steven_lee@aspeedtech.com) Received: from localhost.localdomain (192.168.100.253) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 May 2021 18:03:14 +0800 From: Steven Lee To: Andrew Jeffery , Ulf Hansson , Rob Herring , Joel Stanley , "Adrian Hunter" , Philipp Zabel , Ryan Chen , "moderated list:ASPEED SD/MMC DRIVER" , "moderated list:ASPEED SD/MMC DRIVER" , "open list:ASPEED SD/MMC DRIVER" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ASPEED MACHINE SUPPORT" , open list CC: , , , Subject: [PATCH v3 3/5] ARM: dts: aspeed: ast2600evb: Add phase correction for emmc controller. Date: Thu, 6 May 2021 18:03:10 +0800 Message-ID: <20210506100312.1638-4-steven_lee@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210506100312.1638-1-steven_lee@aspeedtech.com> References: <20210506100312.1638-1-steven_lee@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.100.253] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 1469pSEe024643 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Set MMC timing-phase register by adding the phase correction binding in the device tree. Signed-off-by: Steven Lee Acked-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 1ae0facc3d5f..fa63cb033c57 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -122,7 +122,8 @@ &emmc { non-removable; bus-width = <4>; - max-frequency = <52000000>; + max-frequency = <100000000>; + clk-phase-mmc-hs200 = <9>, <225>; }; &rtc {