From patchwork Mon Dec 20 11:30:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?M=C3=A5rten_Lindahl?= X-Patchwork-Id: 527331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2BC9C41535 for ; Mon, 20 Dec 2021 11:30:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231838AbhLTLam (ORCPT ); Mon, 20 Dec 2021 06:30:42 -0500 Received: from smtp2.axis.com ([195.60.68.18]:53786 "EHLO smtp2.axis.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230476AbhLTLam (ORCPT ); Mon, 20 Dec 2021 06:30:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1639999842; x=1671535842; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZAhJD7nRuyjkg2Akls62NRSlukdDYrMZCbzmafmtA2M=; b=S9QtL5mLa6VQrpe0d2l65i4y5Sa6SulFwN2rfYODUSpXXdPn47b0Z9P5 Llv9Hyn1a09YcU4Aycuz4hj2FmrXf5F+FiFdsIcWN7Y9Gglm4AKm59p+a n+jAqIeHJk7u+jAzdpZxED0/igL1UucSWTizH9JMnfdZqHzUq/cUTKKGU 7h5XBy8BusTFyMv4u1e1mK8UNFv6PIyNLGBSFkmfsslvkxOHT8S92hEKr ozxWWsNYDHgWH12gXRt+alSUv1Zwczr8OZdjVVWgzsTK3NPdyoE9dua6X hiBxYYT9Il6eEh8Fb49AzKyjyAvQax406yaCntG4RyD2qojcYvl4/+HGW A==; From: =?utf-8?q?M=C3=A5rten_Lindahl?= To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Jaehoon Chung CC: Doug Anderson , , , , , , =?utf-8?q?M=C3=A5rten_Lindahl?= Subject: [PATCH v5 3/4] mmc: dw_mmc: Add driver callbacks for data read timeout Date: Mon, 20 Dec 2021 12:30:25 +0100 Message-ID: <20211220113026.21129-4-marten.lindahl@axis.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211220113026.21129-1-marten.lindahl@axis.com> References: <20211220113026.21129-1-marten.lindahl@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Current dw_mci driver supports a TMOUT register which consists of a 24 bit field (TMOUT[31:8]) for the DATA_TIMEOUT. The maximum value of this field is 0xFFFFFF, which with a 200MHz clock will give a full DRTO of: 0xFFFFFF / 200000000 => ~84 ms However, the ARTPEC-8 SoC DWMMC IP version has a TMOUT register with an extended DATA_TIMEOUT field, which supports longer timers for the DRTO. In this version the DATA_TIMEOUT field is split into two, which with the same 200MHz clock as above will allow a maximum timeout of: ((TMOUT[10:8] -1) * 0xFFFFFF + TMOUT[31:11] * 8) / 200000000 => ~587 ms Add driver callbacks for implementation specific data timeout, and implement callback functions for the ARTPEC-8 SoC. Signed-off-by: Mårten Lindahl Acked-by: Krzysztof Kozlowski --- v2: - Removed unnecessary comment - Change 1<<0 to BIT(0) v3: - Add callback for implementation specific control of data timeout - Add callback for implementation specific read of cycle count for data timeout. - Remove definition and use of DW_MMC_QUIRK_EXTENDED_TMOUT. v4: - Add Krzysztof's Acked-by tag from v2 v5: - Remove redundant '0x' prefix from debug message drivers/mmc/host/dw_mmc-exynos.c | 49 ++++++++++++++++++++++++++++++++ drivers/mmc/host/dw_mmc.c | 12 +++++++- drivers/mmc/host/dw_mmc.h | 5 ++++ 3 files changed, 65 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 86486e6659de..3914024cf415 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -539,6 +539,53 @@ static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host, return 0; } +static void dw_mci_exynos_set_data_timeout(struct dw_mci *host, + unsigned int timeout_ns) +{ + u32 clk_div, tmout; + u64 tmp; + unsigned int tmp2; + + clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2; + if (clk_div == 0) + clk_div = 1; + + tmp = DIV_ROUND_UP_ULL((u64)timeout_ns * host->bus_hz, NSEC_PER_SEC); + tmp = DIV_ROUND_UP_ULL(tmp, clk_div); + + /* TMOUT[7:0] (RESPONSE_TIMEOUT) */ + tmout = 0xFF; /* Set maximum */ + + /* + * Extended HW timer (max = 0x6FFFFF2): + * ((TMOUT[10:8] - 1) * 0xFFFFFF + TMOUT[31:11] * 8) + */ + if (!tmp || tmp > 0x6FFFFF2) + tmout |= (0xFFFFFF << 8); + else { + /* TMOUT[10:8] */ + tmp2 = (((unsigned int)tmp / 0xFFFFFF) + 1) & 0x7; + tmout |= tmp2 << 8; + + /* TMOUT[31:11] */ + tmp = tmp - ((tmp2 - 1) * 0xFFFFFF); + tmout |= (tmp & 0xFFFFF8) << 8; + } + + mci_writel(host, TMOUT, tmout); + dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: %#08x", + timeout_ns, tmout >> 8); +} + +static u32 dw_mci_exynos_get_drto_clks(struct dw_mci *host) +{ + u32 drto_clks; + + drto_clks = mci_readl(host, TMOUT) >> 8; + + return (((drto_clks & 0x7) - 1) * 0xFFFFFF) + ((drto_clks & 0xFFFFF8)); +} + /* Common capabilities of Exynos4/Exynos5 SoC */ static unsigned long exynos_dwmmc_caps[4] = { MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA, @@ -564,6 +611,8 @@ static const struct dw_mci_drv_data artpec_drv_data = { .set_ios = dw_mci_exynos_set_ios, .parse_dt = dw_mci_exynos_parse_dt, .execute_tuning = dw_mci_exynos_execute_tuning, + .set_data_timeout = dw_mci_exynos_set_data_timeout, + .get_drto_clks = dw_mci_exynos_get_drto_clks, }; static const struct of_device_id dw_mci_exynos_match[] = { diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index f2a14a434bef..a7745e193afa 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -1287,9 +1287,13 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) static void dw_mci_set_data_timeout(struct dw_mci *host, unsigned int timeout_ns) { + const struct dw_mci_drv_data *drv_data = host->drv_data; u32 clk_div, tmout; u64 tmp; + if (drv_data && drv_data->set_data_timeout) + return drv_data->set_data_timeout(host, timeout_ns); + clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2; if (clk_div == 0) clk_div = 1; @@ -1995,12 +1999,16 @@ static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) static void dw_mci_set_drto(struct dw_mci *host) { + const struct dw_mci_drv_data *drv_data = host->drv_data; unsigned int drto_clks; unsigned int drto_div; unsigned int drto_ms; unsigned long irqflags; - drto_clks = mci_readl(host, TMOUT) >> 8; + if (drv_data && drv_data->get_drto_clks) + drto_clks = drv_data->get_drto_clks(host); + else + drto_clks = mci_readl(host, TMOUT) >> 8; drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2; if (drto_div == 0) drto_div = 1; @@ -2008,6 +2016,8 @@ static void dw_mci_set_drto(struct dw_mci *host) drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, host->bus_hz); + dev_dbg(host->dev, "drto_ms: %u\n", drto_ms); + /* add a bit spare time */ drto_ms += 10; diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 771d5afa3136..0a85d05eaf12 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -556,6 +556,8 @@ struct dw_mci_slot { * @set_ios: handle bus specific extensions. * @parse_dt: parse implementation specific device tree properties. * @execute_tuning: implementation specific tuning procedure. + * @set_data_timeout: implementation specific timeout. + * @get_drto_clks: implementation specific cycle count for data read timeout. * * Provide controller implementation specific extensions. The usage of this * data structure is fully optional and usage of each member in this structure @@ -573,5 +575,8 @@ struct dw_mci_drv_data { struct mmc_ios *ios); int (*switch_voltage)(struct mmc_host *mmc, struct mmc_ios *ios); + void (*set_data_timeout)(struct dw_mci *host, + unsigned int timeout_ns); + u32 (*get_drto_clks)(struct dw_mci *host); }; #endif /* _DW_MMC_H_ */