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Tue, 22 Oct 2024 11:10:29 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 49MBASc7014820; Tue, 22 Oct 2024 11:10:28 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-rampraka-hyd.qualcomm.com [10.213.109.119]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 49MBASBx014819; Tue, 22 Oct 2024 11:10:28 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2305851) id A000657304B; Tue, 22 Oct 2024 16:40:27 +0530 (+0530) From: Ram Prakash Gupta To: Adrian Hunter , Ulf Hansson Cc: linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_cang@quicinc.com, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_sachgupt@quicinc.com, quic_bhaskarv@quicinc.com, quic_narepall@quicinc.com, kernel@quicinc.com Subject: [PATCH 1/1] mmc: sdhci-msm: Toggle the FIFO write clock after ungate Date: Tue, 22 Oct 2024 16:40:25 +0530 Message-Id: <20241022111025.25157-1-quic_rampraka@quicinc.com> X-Mailer: git-send-email 2.17.1 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: E9Ebcoff7Pv7MQGiiOe7l4hoNcK9dFKQ X-Proofpoint-ORIG-GUID: E9Ebcoff7Pv7MQGiiOe7l4hoNcK9dFKQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 clxscore=1011 mlxlogscore=999 phishscore=0 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410220071 Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: For Qualcomm SoCs with sdcc minor version 6B and more, command path state machine is getting corrupted post clock ungate which is leading to software timeout. Toggle the write fifo clock to reset the async fifo to fix this issue. Signed-off-by: Ram Prakash Gupta --- drivers/mmc/host/sdhci-msm.c | 41 ++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index e113b99a3eab..c2ccdac21232 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -146,6 +146,7 @@ /* CQHCI vendor specific registers */ #define CQHCI_VENDOR_CFG1 0xA00 #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN (0x3 << 13) +#define RCLK_TOGGLE BIT(1) struct sdhci_msm_offset { u32 core_hc_mode; @@ -290,6 +291,7 @@ struct sdhci_msm_host { u32 dll_config; u32 ddr_config; bool vqmmc_enabled; + bool toggle_fifo_clk; }; static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host) @@ -1162,6 +1164,39 @@ static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host) return ret; } +/* + * After MCLK ugating, toggle the FIFO write clock to get + * the FIFO pointers and flags to valid state. + */ +static void sdhci_msm_toggle_fifo_write_clk(struct sdhci_host *host) +{ + u32 config; + struct mmc_ios ios = host->mmc->ios; + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + const struct sdhci_msm_offset *msm_offset = msm_host->offset; + + if ((msm_host->tuning_done || ios.enhanced_strobe) && + host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { + /* + * Select MCLK as DLL input clock. + */ + config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3); + config |= RCLK_TOGGLE; + writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_3); + + /* ensure above write as toggling same bit quickly */ + wmb(); + udelay(2); + + /* + * Select RCLK as DLL input clock + */ + config &= ~RCLK_TOGGLE; + writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_3); + } +} + static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable) { const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host); @@ -2587,6 +2622,9 @@ static int sdhci_msm_probe(struct platform_device *pdev) if (core_major == 1 && core_minor >= 0x71) msm_host->uses_tassadar_dll = true; + if (core_major == 1 && core_minor >= 0x6B) + msm_host->toggle_fifo_clk = true; + ret = sdhci_msm_register_vreg(msm_host); if (ret) goto clk_disable; @@ -2720,6 +2758,9 @@ static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev) msm_host->bulk_clks); if (ret) return ret; + + if (msm_host->toggle_fifo_clk) + sdhci_msm_toggle_fifo_write_clk(host); /* * Whenever core-clock is gated dynamically, it's needed to * restore the SDR DLL settings when the clock is ungated.