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[209.132.180.67]) by mx.google.com with ESMTP id uc9si10983844pac.94.2014.03.03.07.09.18; Mon, 03 Mar 2014 07:09:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755048AbaCCPIs (ORCPT + 26 others); Mon, 3 Mar 2014 10:08:48 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:33761 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755013AbaCCPIo (ORCPT ); Mon, 3 Mar 2014 10:08:44 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s23F8JJb030994; Mon, 3 Mar 2014 09:08:19 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s23F8JTs015754; Mon, 3 Mar 2014 09:08:19 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Mon, 3 Mar 2014 09:08:19 -0600 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s23F7Z1F008921; Mon, 3 Mar 2014 09:08:15 -0600 From: Roger Quadros To: , , CC: , , , , , , , , , , Benoit Cousson , Paul Walmsley , Nikhil Devshatwar Subject: [PATCH 11/12] ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods Date: Mon, 3 Mar 2014 17:07:33 +0200 Message-ID: <1393859254-10937-12-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1393859254-10937-1-git-send-email-rogerq@ti.com> References: <1393859254-10937-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rogerq@ti.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Nikhil Devshatwar Add hwmods for ocp2scp3 and sata modules. [Roger Q] Clean up. CC: Benoit Cousson CC: Paul Walmsley Signed-off-by: Balaji T K Signed-off-by: Nikhil Devshatwar Signed-off-by: Roger Quadros --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 41 +++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 18f333c..c180b54 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1215,6 +1215,40 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = { }, }; +/* ocp2scp3 */ +static struct omap_hwmod dra7xx_ocp2scp3_hwmod; +static struct omap_hwmod_addr_space dra7xx_ocp2scp3_addrs[] = { + { + .name = "ocp2scp3", + .pa_start = 0x4a090000, + .pa_end = 0x4a09001f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> ocp2scp3 */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_ocp2scp3_hwmod, + .clk = "l4_root_clk_div", + .addr = dra7xx_ocp2scp3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = { + .name = "ocp2scp3", + .class = &dra7xx_ocp2scp_hwmod_class, + .clkdm_name = "l3init_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + /* * 'qspi' class * @@ -1268,9 +1302,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = { }; /* sata */ -static struct omap_hwmod_opt_clk sata_opt_clks[] = { - { .role = "ref_clk", .clk = "sata_ref_clk" }, -}; static struct omap_hwmod dra7xx_sata_hwmod = { .name = "sata", @@ -1278,6 +1309,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = { .clkdm_name = "l3init_clkdm", .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, .main_clk = "func_48m_fclk", + .mpu_rt_idx = 1, .prcm = { .omap4 = { .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET, @@ -1285,8 +1317,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .opt_clks = sata_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks), }; /* @@ -2683,6 +2713,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per1__mmc4, &dra7xx_l4_cfg__mpu, &dra7xx_l4_cfg__ocp2scp1, + &dra7xx_l4_cfg__ocp2scp3, &dra7xx_l3_main_1__qspi, &dra7xx_l4_cfg__sata, &dra7xx_l4_cfg__smartreflex_core,