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[209.132.180.67]) by mx.google.com with ESMTP id fa4si10878840pbc.238.2014.10.21.05.42.07 for ; Tue, 21 Oct 2014 05:42:07 -0700 (PDT) Received-SPF: none (google.com: linux-omap-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932402AbaJUMmF (ORCPT + 5 others); Tue, 21 Oct 2014 08:42:05 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:47076 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932519AbaJUMmE (ORCPT ); Tue, 21 Oct 2014 08:42:04 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s9LCg1SN019007; Tue, 21 Oct 2014 07:42:01 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s9LCg1Hm018469; Tue, 21 Oct 2014 07:42:01 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Tue, 21 Oct 2014 07:42:00 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s9LCfoo4012514; Tue, 21 Oct 2014 07:41:59 -0500 From: Roger Quadros To: CC: , , , Roger Quadros , Sekhar Nori Subject: [PATCH 4/5] ARM: OMAP2+: gpmc: Keep Chip Select disabled while configuring it Date: Tue, 21 Oct 2014 15:41:48 +0300 Message-ID: <1413895309-9152-5-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413895309-9152-1-git-send-email-rogerq@ti.com> References: <1413895309-9152-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rogerq@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , As per the OMAP reference manual [1], the Chip Select must be disabled (i.e. CSVALID is 0) while configuring any of the Chip select parameters. [1] - 10.1.5.1 Chip-Select Base Address and Region Size Configuration http://www.ti.com/lit/pdf/swpu177 Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori --- arch/arm/mach-omap2/gpmc.c | 34 +++++++++++++++++++++++++++------- 1 file changed, 27 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 0ba95d3..437fb6f 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -397,7 +397,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) return 0; } -static int gpmc_cs_enable_mem(int cs, u32 base, u32 size) +static int gpmc_cs_set_memconf(int cs, u32 base, u32 size) { u32 l; u32 mask; @@ -421,6 +421,15 @@ static int gpmc_cs_enable_mem(int cs, u32 base, u32 size) return 0; } +static void gpmc_cs_enable_mem(int cs) +{ + u32 l; + + l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); + l |= GPMC_CONFIG7_CSVALID; + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); +} + static void gpmc_cs_disable_mem(int cs) { u32 l; @@ -532,18 +541,18 @@ static int gpmc_cs_remap(int cs, u32 base) gpmc_cs_get_memconf(cs, &old_base, &size); if (base == old_base) return 0; - gpmc_cs_disable_mem(cs); + ret = gpmc_cs_delete_mem(cs); if (ret < 0) return ret; + ret = gpmc_cs_insert_mem(cs, base, size); if (ret < 0) return ret; - ret = gpmc_cs_enable_mem(cs, base, size); - if (ret < 0) - return ret; - return 0; + ret = gpmc_cs_set_memconf(cs, base, size); + + return ret; } int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) @@ -572,12 +581,17 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) if (r < 0) goto out; - r = gpmc_cs_enable_mem(cs, res->start, resource_size(res)); + /* Disable CS while changing base address and size mask */ + gpmc_cs_disable_mem(cs); + + r = gpmc_cs_set_memconf(cs, res->start, resource_size(res)); if (r < 0) { release_resource(res); goto out; } + /* Enable CS */ + gpmc_cs_enable_mem(cs); *base = res->start; gpmc_cs_set_reserved(cs, 1); out: @@ -1539,6 +1553,9 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, goto no_timings; } + /* CS must be disabled while making changes to gpmc configuration */ + gpmc_cs_disable_mem(cs); + /* * FIXME: gpmc_cs_request() will map the CS to an arbitary * location in the gpmc address space. When booting with @@ -1577,6 +1594,9 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, val &= ~GPMC_CONFIG_LIMITEDADDRESS; gpmc_write_reg(GPMC_CONFIG, val); + /* Enable CS region */ + gpmc_cs_enable_mem(cs); + no_timings: if (of_platform_device_create(child, NULL, &pdev->dev)) return 0;