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[209.132.180.67]) by mx.google.com with ESMTP id iu8si51483803pbc.58.2015.10.19.02.46.56; Mon, 19 Oct 2015 02:46:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753927AbbJSJqy (ORCPT + 28 others); Mon, 19 Oct 2015 05:46:54 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:57216 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753631AbbJSJqv (ORCPT ); Mon, 19 Oct 2015 05:46:51 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id t9J9kZ7J003257; Mon, 19 Oct 2015 04:46:35 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t9J9kZjD016183; Mon, 19 Oct 2015 04:46:35 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Mon, 19 Oct 2015 04:46:35 -0500 Received: from psplinux063.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t9J9kWt0013049; Mon, 19 Oct 2015 04:46:32 -0500 From: Sekhar Nori To: Thomas Gleixner , Tony Lindgren , Jason Cooper , Marc Zyngier CC: John Ogness , Felipe Balbi , Linux OMAP Mailing List , Subject: [PATCH] irqchip: omap-intc: fix spurious irq handling Date: Mon, 19 Oct 2015 15:16:31 +0530 Message-ID: <3d433cfeeb93366cadbb1668ebeac2e8006b0fd5.1445247844.git.nsekhar@ti.com> X-Mailer: git-send-email 2.4.4.408.g16da57c MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: nsekhar@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.182 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Under some conditions, irq sorting procedure used by INTC can go wrong resulting in a spurious irq getting reported. This condition is flagged by INTC by setting "Spurious IRQ Flag" in SIR register to 0x1ffffff. Section 6.2.5 of AM335x TRM revised Jun 2014 describes this. Using IRQ number 0 for checking this condition is wrong. 0 is a valid INTC IRQ. For example, on AM335x, it is the emulation interrupt. Fix handing of spurious interrupt condition in omap-intc driver by correct detection of spurious interrupt condition. Since spurious IRQ condition can happen under genuine conditions (see the section of AM335x TRM for details) and is recoverable, we do not need a warning splat for users to report. It can however result in reduced performance so we add a ratelimited debug print to aid developers. Signed-off-by: Sekhar Nori --- drivers/irqchip/irq-omap-intc.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-omap-intc.c b/drivers/irqchip/irq-omap-intc.c index 8587d0f8d8c0..739725515fab 100644 --- a/drivers/irqchip/irq-omap-intc.c +++ b/drivers/irqchip/irq-omap-intc.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include /* Define these here for now until we drop all board-files */ #define OMAP24XX_IC_BASE 0x480fe000 @@ -47,6 +49,7 @@ #define INTC_ILR0 0x0100 #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ +#define SPURIOUSIRQ_MASK (0x1ffffff << 7) #define INTCPS_NR_ILR_REGS 128 #define INTCPS_NR_MIR_REGS 4 @@ -333,8 +336,23 @@ omap_intc_handle_irq(struct pt_regs *regs) u32 irqnr; irqnr = intc_readl(INTC_SIR); + + /* + * A spurious IRQ can result if interrupt that triggered the + * sorting is no longer active during the sorting (10 INTC + * functional clock cycles after interrupt assertion). Or a + * change in interrupt mask affected the result during sorting + * time. There is no special handling required except ignoring + * the SIR register value just read and retrying. + * See section 6.2.5 of AM335x TRM Literature Number: SPRUH73K + */ + if ((irqnr & SPURIOUSIRQ_MASK) == SPURIOUSIRQ_MASK) { + pr_debug_ratelimited("%s: spurious irq!\n", __func__); + omap_ack_irq(NULL); + return; + } + irqnr &= ACTIVEIRQ_MASK; - WARN_ONCE(!irqnr, "Spurious IRQ ?\n"); handle_domain_irq(domain, irqnr, regs); }