Message ID | 20240618154306.279637-1-quic_sibis@quicinc.com |
---|---|
Headers | show |
Series | arm64: dts: qcom: x1e80100: Enable bwmon support | expand |
On 6/18/24 17:43, Sibi Sankar wrote: > Document X1E80100 BWMONs, which has multiple (one per cluster) BWMONv4 > instances for the CPU->LLCC path and one BWMONv5 instance for LLCC->DDR > path. Also make the opp-table optional for the X1E cpu-bwmon instances, > since they use the same opp-table between them. > > Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> > --- I think we can just drop the opp-table child node from required altogether, bindings shouldn't care about where the OPP table (which is referenced in the operating-points-v2 property) comes from Konrad
On 6/18/24 17:43, Sibi Sankar wrote: > Add the CPU and LLCC BWMONs on X1E80100 SoCs. > > Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> > --- If you're going to resend, please add a comment like: /* CPU0-3 */ above the respective monitor nodes Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
On 18/06/2024 18:02, Konrad Dybcio wrote: > > > On 6/18/24 17:43, Sibi Sankar wrote: >> Document X1E80100 BWMONs, which has multiple (one per cluster) BWMONv4 >> instances for the CPU->LLCC path and one BWMONv5 instance for LLCC->DDR >> path. Also make the opp-table optional for the X1E cpu-bwmon instances, >> since they use the same opp-table between them. >> >> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> >> --- > > I think we can just drop the opp-table child node from required altogether, > bindings shouldn't care about where the OPP table (which is referenced in > the operating-points-v2 property) comes from I agree. Best regards, Krzysztof