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Tue, 15 Apr 2025 09:54:05 GMT Received: from 087e9057f447.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 15 Apr 2025 02:54:00 -0700 From: Raviteja Laggyshetty To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Odelu Kukatla , Jeff Johnson , Dmitry Baryshkov , Mike Tipton , , , , , "Raviteja Laggyshetty" Subject: [PATCH V11 0/7] Add EPSS L3 provider support on SA8775P SoC Date: Tue, 15 Apr 2025 09:53:36 +0000 Message-ID: <20250415095343.32125-1-quic_rlaggysh@quicinc.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: FEzHkgNgRhzOZFQ7bPJsgvNIT88IcW5f X-Proofpoint-GUID: FEzHkgNgRhzOZFQ7bPJsgvNIT88IcW5f X-Authority-Analysis: v=2.4 cv=ANaQCy7k c=1 sm=1 tr=0 ts=67fe2cbe cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=MOw52E1g2SAjk1dFLq8A:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-15_04,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 mlxlogscore=999 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 spamscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504150069 Add Epoch Subsystem (EPSS) L3 provider support on SA8775P SoCs. Current interconnect framework is based on static IDs for creating node and registering with framework. This becomes a limitation for topologies where there are multiple instances of same interconnect provider. Modified interconnect framework APIs to create and link icc node with dynamic IDs, this will help to overcome the dependency on static IDs. Change since v10: - Removed unused macro OSM_L3_MAX_LINKS - Removed unused arguments from icc_node_create_dyn() function comments Change since v9: - Renamed macro ALLOC_DYN_ID to ICC_ALLOC_DYN_ID. - Added APIs icc_node_create_dyn() and icc_link_nodes() for node creation with dynamic ID allocation and linking. - To optimize the memory, declared the link nodes as double pointer "struct qcom_icc_node **link_nodes" instead of array of pointers "struct qcom_icc_node *link_nodes[MAX_LINKS]". - Added struct icc_node as member in struct qcom_icc_node to help in tracking the node creation and avoid duplicates. Change since v8: - Moved the macro ALLOC_DYN_ID to interconnect.h header. - Declared back the array of pointers and global structs as const in L3 driver. - Separated node creation and node linking in EPSS L3 driver probe, cleaned up unused variables id, links and num_links. - Dropped the opp labels for CPU OPP entries and used (clockrate * buswidth) convention as per review comments. Change since v7: - Updated interconnect framework APIs icc_node_create() and icc_link_create() to dynamically allocate IDs for interconnect nodes during creation. - Moved naming conventions to the framework and replaced snprintf() with devm_kasprintf() as suggested. - Updated the icc-rpmh driver and SA8775P SoC provider driver to support dynamic ID allocation. - Revised commit text to explain the use of the existing generic compatible "qcom,epss-l3". - Addressed other comments regarding the alphabetical ordering of compatible properties. Change since v6: - Added icc_node_create_alloc_id() API to dynamically allocate ID while creating the node. Replaced the IDA (ID allocator) with icc_node_create_alloc_id() API to allocate node IDs dynamically. - Removed qcom,epss-l3-perf generic compatible as per the comment. - Added L3 ICC handles for CPU0 and CPU4 in DT, as per Bjorn comment. Link to comment: https://lore.kernel.org/lkml/ww3t3tu7p36qzlhcetaxif2xzrpgslydmuqo3fqvisbuar4bjh@qc2u43dck3qi/ Change since v5: - Reused qcom,sm8250-epss-l3 compatible for sa8775p SoC. - Rearranged the patches, moved dt changes to end of series. - Updated the commit text. Changes since v4: - Added generic compatible "qcom,epss-l3-perf" and split the driver changes accordingly. Changes since v3: - Removed epss-l3-perf generic compatible changes. These will be posted as separate patch until then SoC specific compatible will be used for probing. Changes since v2: - Updated the commit text to reflect the reason for code change. - Added SoC-specific and generic compatible to driver match table. Changes since v1: - Removed the usage of static IDs and implemented dynamic ID assignment for icc nodes using IDA. - Removed separate compatibles for cl0 and cl1. Both cl0 and cl1 devices use the same compatible. - Added new generic compatible for epss-l3-perf. Jagadeesh Kona (1): arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3 Raviteja Laggyshetty (6): dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P interconnect: core: Add dynamic id allocation support interconnect: qcom: Add multidev EPSS L3 support interconnect: qcom: icc-rpmh: Add dynamic icc node id support interconnect: qcom: sa8775p: Add dynamic icc node id support arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider .../bindings/interconnect/qcom,osm-l3.yaml | 1 + arch/arm64/boot/dts/qcom/sa8775p.dtsi | 229 +++++ drivers/interconnect/core.c | 82 +- drivers/interconnect/qcom/icc-rpmh.c | 17 +- drivers/interconnect/qcom/icc-rpmh.h | 5 + drivers/interconnect/qcom/osm-l3.c | 38 +- drivers/interconnect/qcom/sa8775p.c | 952 +++++++----------- include/linux/interconnect-provider.h | 12 + include/linux/interconnect.h | 3 + 9 files changed, 704 insertions(+), 635 deletions(-)