From patchwork Tue Oct 29 16:44:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 178033 Delivered-To: patches@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp51744ill; Tue, 29 Oct 2019 09:44:47 -0700 (PDT) X-Received: by 2002:ac2:4a8f:: with SMTP id l15mr3093983lfp.5.1572367487508; Tue, 29 Oct 2019 09:44:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1572367487; cv=none; d=google.com; s=arc-20160816; b=S8/32hYkv4PmqsM7zy//tMV2usHytxT/RuyxleZFiboJfCoND1f9XxMKIw0xqK8pJs 0nzkSZ/atdP37alTcAjHeoziYHqD7C7So41S8nAX1mdVe7GGYZ9NBljYweXQVugunTWK 9YErSusJ5Gd6FSg8amWDJO8kqD/RsGO0OWCCpjWyZiwMitZS0OUy2B1iGO9dMr6PiBoe xTLBYwbhioURcmEKzjWiU7CwI/vHwiWIpJMhc8eWB14mJ7qkopNIWs+XwBbstCPgkI2e lv/YQKeaP99od3mYsLKCKnlcnFARCxVv+MseCFQ44VjifZPdYsO9hgCTblBuFwZeen+w UmbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vx1yeiYtbxdfUZEGLcn/GapdFgHrvVzZj2LYjH6Qipc=; b=UE294yNl4DlBWcuuD1nMxlv03eEpE247PxZwAMiUsD3JIzbUtycgYaeENBAIdz20SP 8KqBS5JWWX+a3OSUwtYU/VPMhEc/m4CJykkTohNvg60W1rEbWxCwtBQsiI8ScxCxJLY9 bIlWgk8+lIAIVsoXtXnyFyqfsH9wX73Xr4Ud8W+SLGafw9gZZuzVg2M6Wew1BDOk/iiz Jlru6Ua5PAu4Pw4LL/KYqwG5SpmOy0kKOURIRrWW4YxjMY2uQvQV4LOV5ho5+AJu0ZJE PP1938imudnbxaf8Z667r3ShtgvnfsrqwqRANNTGKSfiy1AGEjfLqT+Bn0Nv7TE2u6yt SwhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Fkoxqmi5; spf=pass (google.com: domain of ulf.hansson@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=ulf.hansson@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id j21sor8221304lja.9.2019.10.29.09.44.47 for (Google Transport Security); Tue, 29 Oct 2019 09:44:47 -0700 (PDT) Received-SPF: pass (google.com: domain of ulf.hansson@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Fkoxqmi5; spf=pass (google.com: domain of ulf.hansson@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=ulf.hansson@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vx1yeiYtbxdfUZEGLcn/GapdFgHrvVzZj2LYjH6Qipc=; b=Fkoxqmi5obbN5D8KiED0GDf2VMvl+yGRap5u5DvS5arveZdlAQDAPXHdayL1+WTok+ LGYVQ5ILzMpoernOY5Qd/dwjKhlBMWBdUZc2ODopoU7NPU7oxthRe3fTPkiS4Ft+Lc7m aE4wxkchBGDMleSnkmLrCtgti0b75RN6qyqJOq0+czV+kJi5lyJxPrAmjBF5DWFjVrT1 2azq3w9IMJTYkkt6CIu771rCLj+N2TpEQmLMav3yvsenOsefdWc3jpS/3tf/6xDPR5Le 84RHvn18prIrS2TSR/gWIuDE5MWjam+6gHZMAsfRCEvpfq3NJ6nDTU9pWFbdLBFKmqR1 nP9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vx1yeiYtbxdfUZEGLcn/GapdFgHrvVzZj2LYjH6Qipc=; b=iJrisVbnv42vDLjvQPvbsJeFw+Y8TbVSnYEXZ2Qh6YKl9sn0iZphjUqeJiGk4T6Kbr Eyb1sLf38q4KlCXkVilMSG2I0JyHbpocqTp3Vcaj5Lgrsn/W9B8LaZ4L7EQgiCZcYAVM boZQi9n57bard5dkvURD8rXrKh5bz8jYEjtLeNdye1fBse70WFDDpRymN/VSHxtqNUOQ xBCq/pCadaabADoOarVgrgAECThZ0xynDgchHc048QPzV7b9tx1r/2NUnk9S4gg61Vjo R56V0waqUV9Z1D1ANmUseFywCircIVMkdfnLWDEcee71G2mN1wnIgg66/tTrRPk7oqCL +60g== X-Gm-Message-State: APjAAAXTaEb54hP+6L4lxixJ7LxXM74OWq9guNI0oYnDte8kD/sNtvhy QHhgtrrkBfxr5SGfqzcw6HdKIT/G X-Google-Smtp-Source: APXvYqzNAJhOXSwzgS3m1Z95FU4/bc2E3nX7fJG9+SlaGXQA0RhR9Fs7yJqz8IEOfLNRvwR9bzPwxw== X-Received: by 2002:a2e:b607:: with SMTP id r7mr3349557ljn.47.1572367487022; Tue, 29 Oct 2019 09:44:47 -0700 (PDT) Return-Path: Received: from localhost.localdomain (h-158-174-22-210.NA.cust.bahnhof.se. [158.174.22.210]) by smtp.gmail.com with ESMTPSA id f28sm2048161lfh.35.2019.10.29.09.44.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2019 09:44:46 -0700 (PDT) From: Ulf Hansson To: "Rafael J . Wysocki" , Daniel Lezcano , Sudeep Holla , Lorenzo Pieralisi , Mark Rutland , Lina Iyer , linux-pm@vger.kernel.org Cc: Rob Herring , Vincent Guittot , Stephen Boyd , Andy Gross , Bjorn Andersson , Kevin Hilman , Ulf Hansson , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Lina Iyer Subject: [PATCH v2 02/13] dt: psci: Update DT bindings to support hierarchical PSCI states Date: Tue, 29 Oct 2019 17:44:27 +0100 Message-Id: <20191029164438.17012-3-ulf.hansson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191029164438.17012-1-ulf.hansson@linaro.org> References: <20191029164438.17012-1-ulf.hansson@linaro.org> Update PSCI DT bindings to allow to represent idle states for CPUs and the CPU topology, by using a hierarchical layout. Primarily this is done by re-using the existing DT bindings for PM domains [1] and for PM domain idle states [2]. Let's also add an example into the document for the PSCI DT bindings, to clearly show the new hierarchical based layout. The currently supported flattened layout, is already described in the ARM idle states bindings [3], so let's leave that as is. [1] Documentation/devicetree/bindings/power/power_domain.txt [2] Documentation/devicetree/bindings/power/domain-idle-state.txt [3] Documentation/devicetree/bindings/arm/idle-states.txt Co-developed-by: Lina Iyer Signed-off-by: Lina Iyer Signed-off-by: Ulf Hansson --- Changes in v2: - Clarifications and also added updates cpus.yaml, to descrive that CPUs may be attached to PM domains. --- .../devicetree/bindings/arm/cpus.yaml | 15 +++ .../devicetree/bindings/arm/psci.yaml | 102 ++++++++++++++++++ 2 files changed, 117 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index cb30895e3b67..92a775d6fc0e 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -241,6 +241,21 @@ properties: where voltage is in V, frequency is in MHz. + power-domains: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: + List of phandles and PM domain specifiers, as defined by bindings of the + PM domain provider (see also ../power_domain.txt). + + power-domain-names: + $ref: '/schemas/types.yaml#/definitions/string-array' + description: + A list of power domain name strings sorted in the same order as the + power-domains property. + + For PSCI based platforms, the name corresponding to the index of the PSCI + PM domain provider, must be "psci". + qcom,saw: $ref: '/schemas/types.yaml#/definitions/phandle' description: | diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml index 7abdf58b335e..9fed255cc92d 100644 --- a/Documentation/devicetree/bindings/arm/psci.yaml +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -102,6 +102,34 @@ properties: [1] Kernel documentation - ARM idle states bindings Documentation/devicetree/bindings/arm/idle-states.txt + "#power-domain-cells": + description: + The number of cells in a PM domain specifier as per binding in [3]. + Must be 0 as to represent a single PM domain. + + ARM systems can have multiple cores, sometimes in an hierarchical + arrangement. This often, but not always, maps directly to the processor + power topology of the system. Individual nodes in a topology have their + own specific power states and can be better represented hierarchically. + + For these cases, the definitions of the idle states for the CPUs and the + CPU topology, must conform to the binding in [3]. The idle states + themselves must conform to the binding in [4] and must specify the + arm,psci-suspend-param property. + + It should also be noted that, in PSCI firmware v1.0 the OS-Initiated + (OSI) CPU suspend mode is introduced. Using a hierarchical representation + helps to implement support for OSI mode and OS implementations may choose + to mandate it. + + [3] Documentation/devicetree/bindings/power/power_domain.txt + [4] Documentation/devicetree/bindings/power/domain-idle-state.txt + + power-domains: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: + List of phandles and PM domain specifiers, as defined by bindings of the + PM domain provider. required: - compatible @@ -160,4 +188,78 @@ examples: cpu_on = <0x95c10002>; cpu_off = <0x95c10001>; }; + + - |+ + + // Case 4: CPUs and CPU idle states described using the hierarchical model. + + cpus { + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + }; + + idle-states { + + CPU_PWRDN: cpu-power-down { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + + CLUSTER_RET: cluster-retention { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000011>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWRDN: cluster-power-down { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000031>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; + }; + }; ...