From patchwork Mon May 18 09:24:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Lu X-Patchwork-Id: 212012 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86D8CC433E0 for ; Mon, 18 May 2020 09:25:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 60E6A20787 for ; Mon, 18 May 2020 09:25:00 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Mon, 18 May 2020 17:24:51 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 18 May 2020 17:24:47 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 18 May 2020 17:24:47 +0800 From: Roger Lu To: Kevin Hilman , Rob Herring , Nicolas Boichat , Stephen Boyd CC: Fan Chen , HenryC Chen , YT Lee , Xiaoqing Liu , Charles Yang , Angus Lin , Mark Rutland , Matthias Brugger , Nishanth Menon , Roger Lu , , , , , Subject: [PATCH v8 2/3] arm64: dts: mt8183: add svs device information Date: Mon, 18 May 2020 17:24:03 +0800 Message-ID: <20200518092403.22647-3-roger.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200518092403.22647-1-roger.lu@mediatek.com> References: <20200518092403.22647-1-roger.lu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 470799B14A663516422E7C38CC9E7744BC9531C9C7DF9683D475CD2044EBF24B2000:8 X-MTK: N Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org add pmic/clock/irq/efuse setting in svs node Signed-off-by: Roger Lu --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 16 ++++++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 41 +++++++++++++++++++++ 2 files changed, 57 insertions(+) reg = <0 0x1100f000 0 0x1000>, @@ -644,6 +677,14 @@ compatible = "mediatek,mt8183-efuse", "mediatek,efuse"; reg = <0 0x11f10000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + thermal_calibration: calib@180 { + reg = <0x180 0xc>; + }; + svs_calibration: calib@580 { + reg = <0x580 0x64>; + }; }; mfgcfg: syscon@13000000 { -- 2.18.0 diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 1fb195c683c3..6ae1d9a1bcbf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -231,6 +231,22 @@ }; }; +&svs_cpu_little { + vcpu-little-supply = <&mt6358_vproc12_reg>; +}; + +&svs_cpu_big { + vcpu-big-supply = <&mt6358_vproc11_reg>; +}; + +&svs_cci { + vcci-supply = <&mt6358_vproc12_reg>; +}; + +&svs_gpu { + vgpu-spply = <&mt6358_vgpu_reg>; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 97863adb7bc0..6b6b8dc1824f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -453,6 +453,39 @@ status = "disabled"; }; + svs: svs@1100b000 { + compatible = "mediatek,mt8183-svs"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calibration>, + <&thermal_calibration>; + nvmem-cell-names = "svs-calibration-data", + "calibration-data"; + + svs_cpu_little: svs-cpu-little { + compatible = "mediatek,mt8183-svs-cpu-little"; + operating-points-v2 = <&cluster0_opp>; + }; + + svs_cpu_big: svs-cpu-big { + compatible = "mediatek,mt8183-svs-cpu-big"; + operating-points-v2 = <&cluster1_opp>; + }; + + svs_cci: svs-cci { + compatible = "mediatek,mt8183-svs-cci"; + operating-points-v2 = <&cci_opp>; + }; + + svs_gpu: svs-gpu { + compatible = "mediatek,mt8183-svs-gpu"; + power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_2D>; + operating-points-v2 = <&gpu_opp_table>; + }; + }; + i2c3: i2c@1100f000 { compatible = "mediatek,mt8183-i2c";