From patchwork Wed Oct 19 13:59:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 616653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DA71C433FE for ; Wed, 19 Oct 2022 14:18:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232452AbiJSOSe (ORCPT ); Wed, 19 Oct 2022 10:18:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233355AbiJSOSH (ORCPT ); Wed, 19 Oct 2022 10:18:07 -0400 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4380E1413BC for ; Wed, 19 Oct 2022 07:01:08 -0700 (PDT) Received: by mail-pf1-x429.google.com with SMTP id d10so17310761pfh.6 for ; Wed, 19 Oct 2022 07:01:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+OcwfXiesFKWlB7LNMDAzT3rAd6eUuEjWbfk2IH0mpk=; b=WA4KMdnBVL+ZMwm+rEVukf179/vk4fY9BLq2BQFrgdNIP/gBlttSSFWfZOXXHipikE +FbOZJ8ahiKF6DjWe5751c36vgaU0gspOSriB9aUmz1RX2M5mwu85HExLQ88E9A1MAqQ /rwj5ezqYcL4TWLKIVHzbXNWoffwR5jr4CHoWynxtsjmAXb7gzAGrv7HVGcBTlLd45JQ w2jtZqXJPlwQB/xOzpjV9uy+tYKajnM6VU4khlHr+OKDe51QKqEBmXcWHFL+R17G3CMo L3TApDSeHHPxLJJWTofj6QcKH2bQ9oOErlB+6GlkbPXnTLVao2o4TsSWvNTnOAq9vakv TGaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+OcwfXiesFKWlB7LNMDAzT3rAd6eUuEjWbfk2IH0mpk=; b=jhBSajQuujbxlECg0xVhDrRoqIUHdgtL9I/MC3/zqBha7d6QmfDM3THMzO9fxJ6IXG epS9Vx+xBhQ2H1/ON9v7ibAk/a9nCsX7HEEfmd7IafdjQ9Wd+0hcmaV2ZUz+4vLIvFRO ujfiZdXxSp971vvH8htB3ddoY0wiDUo0ZdgB0tbMmH5fMPhNfEyuQyAP5ISb4TXDHHVz 24avKkj5R6PUR/hL3xVjTIfYLLuRqX1/ssxpyQnaxXRWWHyxgoMQK/FXSbW3c8zM9LPW 5IRVTbFwo7pU2fSW4E3ZJH53wpkxCNl1R5/oMtnAZulDqKGzjkcYU8tc85Nq17ueldqb qLyA== X-Gm-Message-State: ACrzQf0AUbtOY96xa7mQYoYiw8iFBfG4lFtViWhujpXrqYJBeP6JeYfC LFfMIQQQ6MfQHnvye0/HTzYY X-Google-Smtp-Source: AMsMyM7f6bse5t+spGebFFBq804fQPJYGEZ1hTju7FWBhrPdATCipPsJ5yDh6jmvaexhcCfdO/KnpA== X-Received: by 2002:a05:6a00:15ce:b0:562:cafb:2844 with SMTP id o14-20020a056a0015ce00b00562cafb2844mr8781505pfu.75.1666187988528; Wed, 19 Oct 2022 06:59:48 -0700 (PDT) Received: from localhost.localdomain ([117.193.210.93]) by smtp.gmail.com with ESMTPSA id 194-20020a6216cb000000b0053e199aa99bsm11240322pfw.220.2022.10.19.06.59.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 06:59:47 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 2/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add cpufreq clock provider Date: Wed, 19 Oct 2022 19:29:23 +0530 Message-Id: <20221019135925.366162-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221019135925.366162-1-manivannan.sadhasivam@linaro.org> References: <20221019135925.366162-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. Document the same in the binding to reflect the actual implementation. CPUFreq HW will become the clock provider and CPU cores will become the clock consumers. The clock index for each CPU core is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- .../devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index cbba8979fe0e..2e0336163ffb 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -57,6 +57,9 @@ properties: '#freq-domain-cells': const: 1 + '#clock-cells': + const: 1 + required: - compatible - reg @@ -84,6 +87,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -100,6 +104,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -113,6 +118,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -126,6 +132,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -139,6 +146,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -152,6 +160,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -165,6 +174,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -178,6 +188,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -198,6 +209,7 @@ examples: clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; }; ...