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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id o24-20020a056512051800b004a2c447598fsm2182944lfb.159.2023.03.07.17.27.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 17:27:26 -0800 (PST) From: Konrad Dybcio Date: Wed, 08 Mar 2023 02:27:04 +0100 Subject: [PATCH 7/8] arm64: dts: qcom: sm6350: Add SoC-specific compatible to cpufreq_hw MIME-Version: 1.0 Message-Id: <20230308-topic-cpufreq_bindings-v1-7-3368473ec52d@linaro.org> References: <20230308-topic-cpufreq_bindings-v1-0-3368473ec52d@linaro.org> In-Reply-To: <20230308-topic-cpufreq_bindings-v1-0-3368473ec52d@linaro.org> To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam , Andy Gross , Bjorn Andersson Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678238834; l=831; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=+CETfRtA+2dftHc8AjtHAgxUAslRxj6c2rgtY/K3MCM=; b=1Cok6m8m/10QMMyHcZsY7afVxCNFdOabAQIebdgi2ivqUtBwBa4T/cynfRcKo7KxvQEi59S0OosR Y7MA/jV8AG6NrYM40LFINQgQsJZXIMhQl9JQSj2rV7HQ3WvYZUE8 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 1e1d366c92c1..c18ca947618e 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1995,7 +1995,7 @@ osm_l3: interconnect@18321000 { }; cpufreq_hw: cpufreq@18323000 { - compatible = "qcom,cpufreq-hw"; + compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;