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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id a18-20020a05651c011200b002b32af2e9c6sm901490ljb.116.2023.06.13.07.03.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 07:03:23 -0700 (PDT) From: Konrad Dybcio Date: Tue, 13 Jun 2023 16:03:08 +0200 Subject: [PATCH v4 08/22] interconnect: qcom: smd-rpm: Add rpmcc handling skeleton code MIME-Version: 1.0 Message-Id: <20230526-topic-smd_icc-v4-8-5ba82b6fbba2@linaro.org> References: <20230526-topic-smd_icc-v4-0-5ba82b6fbba2@linaro.org> In-Reply-To: <20230526-topic-smd_icc-v4-0-5ba82b6fbba2@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Georgi Djakov , Leo Yan , Evan Green , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686664985; l=3310; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=iZtmW6P5itI9VHLGXoDENCykQOqQdEmcRxdn0VZPg6E=; b=luBagDShG4+0IcCihhHd6K0sAmFhvXnydeNLGUeiSpmEk0ip+lPyGwgIse74PwI8oWg3KUBL5 fckV4XJ0iwXAh6uSmviP5q8O9q1lPBDTvQk6+INWEt9MkYfB5Mz3Zw/ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce qcom_icc_rpm_set_bus_rate() in preparation for handling RPM clock resources within the interconnect framework. This lets us greatly simplify all of the code handling, as setting the rate comes down to: u32 rate_khz = max(clk.sleep_rate, clk.active_rate, clk_a.active_rate) write_to_rpm(clock.description, rate_khz); Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/icc-rpm.h | 15 +++++++++++++++ drivers/interconnect/qcom/smd-rpm.c | 22 ++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index 9ec90e13bfbd..13ca0818ffbd 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -22,6 +22,18 @@ enum qcom_icc_type { QCOM_ICC_QNOC, }; +/** + * struct rpm_clk_resource - RPM bus clock resource + * @resource_type: RPM resource type of the clock resource + * @clock_id: index of the clock resource of a specific resource type + * @branch: whether the resource represents a branch clock +*/ +struct rpm_clk_resource { + u32 resource_type; + u32 clock_id; + bool branch; +}; + #define NUM_BUS_CLKS 2 /** @@ -47,6 +59,7 @@ struct qcom_icc_provider { unsigned int qos_offset; u64 bus_clk_rate[NUM_BUS_CLKS]; struct clk_bulk_data bus_clks[NUM_BUS_CLKS]; + const struct rpm_clk_resource *bus_clk_desc; struct clk_bulk_data *intf_clks; bool keep_alive; bool is_on; @@ -104,6 +117,7 @@ struct qcom_icc_desc { struct qcom_icc_node * const *nodes; size_t num_nodes; const char * const *bus_clocks; + const struct rpm_clk_resource *bus_clk_desc; const char * const *intf_clocks; size_t num_intf_clocks; bool keep_alive; @@ -125,5 +139,6 @@ int qnoc_remove(struct platform_device *pdev); bool qcom_icc_rpm_smd_available(void); int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val); +int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, u32 rate, bool set_active); #endif diff --git a/drivers/interconnect/qcom/smd-rpm.c b/drivers/interconnect/qcom/smd-rpm.c index b0183262ba66..c5ab00051447 100644 --- a/drivers/interconnect/qcom/smd-rpm.c +++ b/drivers/interconnect/qcom/smd-rpm.c @@ -16,6 +16,7 @@ #include "icc-rpm.h" #define RPM_KEY_BW 0x00007762 +#define QCOM_RPM_SMD_KEY_RATE 0x007a484b static struct qcom_smd_rpm *icc_smd_rpm; @@ -44,6 +45,27 @@ int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val) } EXPORT_SYMBOL_GPL(qcom_icc_rpm_smd_send); +int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, u32 rate, bool set_active) +{ + int state = set_active ? QCOM_SMD_RPM_ACTIVE_STATE : QCOM_SMD_RPM_SLEEP_STATE; + struct clk_smd_rpm_req req = { + .key = cpu_to_le32(QCOM_RPM_SMD_KEY_RATE), + .nbytes = cpu_to_le32(sizeof(u32)), + }; + + /* Branch clocks are only on/off */ + if (clk->branch) + rate = !!rate; + + req.value = cpu_to_le32(rate); + return qcom_rpm_smd_write(icc_smd_rpm, + state, + clk->resource_type, + clk->clock_id, + &req, sizeof(req)); +} +EXPORT_SYMBOL_GPL(qcom_icc_rpm_set_bus_rate); + static int qcom_icc_rpm_smd_remove(struct platform_device *pdev) { icc_smd_rpm = NULL;