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[83.9.2.185]) by smtp.gmail.com with ESMTPSA id j20-20020ac253b4000000b004fbdba4b075sm1861679lfh.57.2023.08.08.04.43.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Aug 2023 04:43:47 -0700 (PDT) From: Konrad Dybcio Date: Tue, 08 Aug 2023 13:43:41 +0200 Subject: [PATCH v3 10/10] clk: qcom: smd-rpm: Move CPUSS_GNoC clock to interconnect MIME-Version: 1.0 Message-Id: <20230726-topic-icc_coeff-v3-10-dee684d6cdd2@linaro.org> References: <20230726-topic-icc_coeff-v3-0-dee684d6cdd2@linaro.org> In-Reply-To: <20230726-topic-icc_coeff-v3-0-dee684d6cdd2@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Michael Turquette , Stephen Boyd Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1691495013; l=1855; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=6rZrHWsPHWWpd+L+pVqcUMQuVU01TmS5LCQGYAT1X0Q=; b=jtBpHrfD+ymd4XqtHtbF/noRNPMY58C9Ej/e6oBO74GRvFvp0xnbWwQis4SQSnKJbpvuAezcV O1Vfy8GohTlAwg/NRNh5jnTxAmB6T34tNgUqWUBA1EdFDKu7EABgkpv X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org As it turns out, it's yet another interconnect bus clock. Move it there. See [1] for reference. [1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/02f8c342b23c20a5cf967df649814be37a08227c%5E%21/#F0 Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/clk-smd-rpm.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 9b5411932594..4a23f6d3eddd 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -567,6 +567,16 @@ static const struct clk_smd_rpm *sm_qnoc_icc_clks[] = { &clk_smd_rpm_bus_2_snoc_clk, }; +static const struct clk_smd_rpm *qcm2290_icc_clks[] = { + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_bus_1_cnoc_clk, + &clk_smd_rpm_mmnrt_clk, + &clk_smd_rpm_mmrt_clk, + &clk_smd_rpm_qup_clk, + &clk_smd_rpm_bus_2_snoc_clk, + &clk_smd_rpm_cpuss_gnoc_clk, +}; + static struct clk_smd_rpm *msm8909_clks[] = { [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, @@ -1182,15 +1192,13 @@ static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk, [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, - [RPM_SMD_CPUSS_GNOC_CLK] = &clk_smd_rpm_cpuss_gnoc_clk, - [RPM_SMD_CPUSS_GNOC_A_CLK] = &clk_smd_rpm_cpuss_gnoc_a_clk, }; static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = { .clks = qcm2290_clks, .num_clks = ARRAY_SIZE(qcm2290_clks), - .icc_clks = sm_qnoc_icc_clks, - .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks) + .icc_clks = qcm2290_icc_clks, + .num_icc_clks = ARRAY_SIZE(qcm2290_icc_clks) }; static const struct of_device_id rpm_smd_clk_match_table[] = {