From patchwork Sat Feb 3 04:05:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 770281 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41F6E1118E; Sat, 3 Feb 2024 04:04:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933049; cv=none; b=RAoWzbenFhp0TUS7L+AK/iTtMhU5xqZbefBd6PRZP1Ty7iXf8289f/Syxcf87fyzuIO6XUpYLxcHIHswjlQE3pOR1uY9Wx5Zj/nxvmeRkIG7hUWR4d4mpE47imXS+TGhLnPGEW7Lhk8mtrM2gE6Kx+08YdUIPTQzJuRE4LSeOnw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933049; c=relaxed/simple; bh=tPRApoSMpWENCgHFmpqWBaJZ2dE2sWiZiCQc9GL+JjM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=NrudZEWEGeH0VPhKDZ1pdvpcflhlgzBFB/XxzGJID4kw/yxsSybB3nZsyyRxt2Z5mi7+oBdeLVbaBEUbvVpJDa10sDixR1K6LencxNjLyNfSDwXRsyLgEyHlEOr6cv+SnC73Vm2ooGYwrGheZ41ueJyy0jq9rTcKB+WhXVQU1IA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=afX2aAjk; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="afX2aAjk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706933048; x=1738469048; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=tPRApoSMpWENCgHFmpqWBaJZ2dE2sWiZiCQc9GL+JjM=; b=afX2aAjkOfwaueMyp9j7cKzUj3/E96MvypnEnOTkMe+aiu30OowaQioX WFKImsflvZT5OerpcbVRexIhfphsXKicAIi/wcVt/RJaHxMLG03j2n/We p7+jBQLo4SqvMMvzYQKVh4U3+LpPxYoQJ4GizlQptdumx/HHeITAenzpz o06qDd4/y5vZScYGVZ/wowgy6fZwEcFGXMXTS9QUtXsISR/f4CFim3CKA m7t2aYnpHLXu6UcFxnCX3Rb5KePGwT2Zt+NIA5P3MQY/Q/cIjgtPz8Pq0 y5T6fRunNGBk1pOoh1yvpu6FnK1dL6lQGei28QjYNOBcmJRBCygFaaI8h w==; X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="4181425" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="4181425" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2024 20:04:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="823382525" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="823382525" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga001.jf.intel.com with ESMTP; 02 Feb 2024 20:04:05 -0800 From: Ricardo Neri To: "Rafael J. Wysocki" Cc: Len Brown , Srinivas Pandruvada , Stanislaw Gruszka , Zhao Liu , Zhuocheng Ding , x86@kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Zhao Liu Subject: [PATCH 7/9] x86/cpufeatures: Add feature bit for HRESET Date: Fri, 2 Feb 2024 20:05:13 -0800 Message-Id: <20240203040515.23947-8-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> References: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The HRESET instruction isolates the classification of individual tasks when they run sequentially on the same logical processor. It resets the classification history that the logical processor maintains. Cc: Len Brown Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Stanislaw Gruszka Cc: Zhao Liu Cc: Zhuocheng Ding Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Patch cherry-picked from the IPC classes patchset. --- --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 8104f4791abd..3b42479c049d 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -326,6 +326,7 @@ #define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */ #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ +#define X86_FEATURE_HRESET (12*32+22) /* Hardware history reset instruction */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ #define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index d74932a0778d..65b1bfb9c304 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1155,6 +1155,9 @@ #define MSR_IA32_HW_FEEDBACK_CHAR 0x17d2 +/* Hardware History Reset */ +#define MSR_IA32_HW_HRESET_ENABLE 0x17da + /* x2APIC locked status */ #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD #define LEGACY_XAPIC_DISABLED BIT(0) /*