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Fri, 18 Oct 2024 05:49:44 -0700 (PDT) From: Bartosz Golaszewski Date: Fri, 18 Oct 2024 14:49:16 +0200 Subject: [PATCH v6 6/6] arm64: dts: qcom: sm8450-hdk: model the PMU of the on-board wcn6855 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241018-sc8280xp-pwrseq-v6-6-8da8310d9564@linaro.org> References: <20241018-sc8280xp-pwrseq-v6-0-8da8310d9564@linaro.org> In-Reply-To: <20241018-sc8280xp-pwrseq-v6-0-8da8310d9564@linaro.org> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Bjorn Andersson , Konrad Dybcio , Johan Hovold , Kalle Valo , Dmitry Baryshkov , Abel Vesa , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5563; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=1R0dZeOAv50eWbW4Hszj2kUWLcatmibvSfqEpRoAU7g=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBnEllgjbd04ztjzNExSs78CJOOz337EN0NxtRd/ 6gbQKZKbQaJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCZxJZYAAKCRARpy6gFHHX ch9mEADBKXRTjzn7x8VnOkmoocbJwx64bVMcwPh/++m2yzmBzTYKWIiwWrB7R8Ely+i6yH75N0G TEzdL22l49vqCuAKbnegOKtBLnhn8pDheNcnaLLDYU46aDwZIDLwGnRWVroEOizyZTDb/IaFEsf mQ+LSu77Via9GacpG5/UgMlxhxuxP6lEO95y+FnYPOx7PlKLnu/PkdPlH3NrGmLGTofa+FOSspm qTVyT3CPQesxgSTYlcx6wLHkZ+YSV303q+GYCXh3zIG4BzDGe1jTEP+RW/Gad/QeUbWYMhuwoIY bpMk7KxNIpQxmGGoJ7yrK7i1ykdb79auFjNePh9DsBnPFptJkEjqxjwTy1LpCUMOHSbpWpfhNjT dlurZvNDmx0aeMxeObhq3yR8/ZjpTMLLTiWeFLlW84JN4ES5Djix2EDVDMCdoOBJjbNkyYOsLID KW+bLfXEfC/RNFofJhYmW/UTbLMg9n/LSi0xlGSVmeEcnoPNjT3DT+jW2+8akBaZ9e5QYMPGJkG PqLjKONZIZsrs4c3UPNO6OfziRdpAb3rB+BPc3CazgDHAbImkJH8Yor7LAT33osfUWkf6d7zH5Q NJcTCrerA4ERcNub+h7JGId1Nt3BPY8kLQrIcdtiMW25/s/MMGQlmwc78GOLggdCPCbNlqe1x8B O9WGTT60S76XGAA== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Add nodes for the WCN6855 PMU, the WLAN and BT modules and relevant regulators and pin functions to fully describe how the wifi is actually wired on this platform. Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 157 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 2 files changed, 158 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 67443822653d..2ff40a120aad 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -26,6 +26,7 @@ / { aliases { serial0 = &uart7; + serial1 = &uart20; }; wcd938x: audio-codec { @@ -247,6 +248,71 @@ active-config0 { }; }; + wcn6855-pmu { + compatible = "qcom,wcn6855-pmu"; + + pinctrl-0 = <&bt_en>, <&wlan_en>, <&xo_clk_default>; + pinctrl-names = "default"; + + wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>; + xo-clk-gpios = <&tlmm 204 GPIO_ACTIVE_HIGH>; + + vddio-supply = <&vreg_s10b_1p8>; + vddaon-supply = <&vreg_s11b_0p95>; + vddpmu-supply = <&vreg_s12b_1p25>; + vddpmumx-supply = <&vreg_s2e_0p85>; + vddpmucx-supply = <&vreg_s11b_0p95>; + vddrfa0p95-supply = <&vreg_s11b_0p95>; + vddrfa1p3-supply = <&vreg_s12b_1p25>; + vddrfa1p9-supply = <&vreg_s1c_1p86>; + vddpcie1p3-supply = <&vreg_s12b_1p25>; + vddpcie1p9-supply = <&vreg_s1c_1p86>; + + regulators { + vreg_pmu_rfa_cmn_0p8: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn_0p8"; + }; + + vreg_pmu_aon_0p8: ldo1 { + regulator-name = "vreg_pmu_aon_0p8"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p8: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p8"; + }; + + vreg_pmu_btcmx_0p8: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p8"; + }; + + vreg_pmu_pcie_1p8: ldo5 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo6 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_rfa_0p8: ldo7 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo8 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo9 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -685,6 +751,23 @@ &pcie0_phy { vdda-pll-supply = <&vreg_l6b_1p2>; }; +&pcieport0 { + wifi@0 { + compatible = "pci17cb,1103"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; + vddaon-supply = <&vreg_pmu_aon_0p8>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + }; +}; + &pcie1 { status = "okay"; }; @@ -892,6 +975,10 @@ &qupv3_id_1 { status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &sdhc_2 { cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; pinctrl-names = "default", "sleep"; @@ -1069,6 +1156,26 @@ &uart7 { status = "okay"; }; +&uart20 { + pinctrl-0 = <&uart20_default>; + pinctrl-names = "default"; + + status = "okay"; + + bluetooth { + compatible = "qcom,wcn6855-bt"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; + vddaon-supply = <&vreg_pmu_aon_0p8>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + }; +}; + &ufs_mem_hc { status = "okay"; @@ -1130,6 +1237,14 @@ &vamacro { }; &tlmm { + bt_en: bt-en-state { + pins = "gpio81"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-pull-down; + }; + spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio1"; function = "gpio"; @@ -1153,4 +1268,46 @@ wcd_default: wcd-reset-n-active-state { bias-disable; output-low; }; + + wlan_en: wlan-en-state { + pins = "gpio80"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-pull-down; + }; + + uart20_default: uart20-default-state { + cts-pins { + pins = "gpio76"; + function = "qup20"; + bias-disable; + }; + + rts-pins { + pins = "gpio77"; + function = "qup20"; + bias-disable; + }; + + rx-pins { + pins = "gpio78"; + function = "qup20"; + bias-disable; + }; + + tx-pins { + pins = "gpio79"; + function = "qup20"; + bias-disable; + }; + }; + + xo_clk_default: xo-clk-state { + pins = "gpio204"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-pull-down; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1b5dc5b8cecb..be876a919455 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1880,7 +1880,7 @@ opp-8000000 { }; }; - pcie@0 { + pcieport0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>;