From patchwork Fri Nov 8 06:39:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Tseng X-Patchwork-Id: 842012 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADD9A19DF64; Fri, 8 Nov 2024 06:39:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731047996; cv=none; b=D17UxJEazEX12T8OG3iwkWuJo3yA8Ix4Gb2PIIUWktWnNEuK9DlSVzmOJU9e8+U64mRVSqlVs1RDTUN3xugZ898A/sMFxi2DbIN3gYocZdCNAW8TLAQdhSHxahSPtPiJYoAkdrs7IsrtoS1VVPZTAKHhBdBsqLnJzTCC9WRwVJc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731047996; c=relaxed/simple; bh=ftHl8cvJxXClXUyb+pLcTha+k6Boj0naoJhKG2j7H5o=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cJyq1OcL4qNeXdPbgW4ZA6JXGzMnc66VUp8UPJUjSO7xt0pCbZVjeAL7VlFsp5IY05ExqkXQl9jTY+fnkbHDhfr0VBw0AOL6Cv+rsfucCfXPQEb/tyithlpBw58O89PhlLXI8KVTHiPbZQ7TlXiOIsM662Ptx4j38dQU501RPvY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=SFKN9PIL; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="SFKN9PIL" X-UUID: 40c6c8009d9c11efbd192953cf12861f-20241108 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=H7HqclB1EjyymZaIs5NdapuhMiQdBA7440+mZymKrGw=; b=SFKN9PILuj6x0mTzrjvzbjhlD8L+4s8tG1q7/2CegJdy7IxLdCzgxmOLUtSvgxR8xpcdkN1LKXcnxZ3q1r+cJdxxoq/HTTpQvBljSaxJqXUy0irE/eI+Ju/tqMxhQ/roO5sjA3RuanOg9z0t7Wb8sXFEVNYZtqdGDzGwyHSGLcc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.42, REQID:1bf7bd15-5486-4664-b691-87261006050c, IP:0, U RL:0,TC:0,Content:18,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:18 X-CID-META: VersionHash:b0fcdc3, CLOUDID:76ffb8ca-91e6-4060-9516-6ba489b4e2dc, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:4,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 40c6c8009d9c11efbd192953cf12861f-20241108 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1531420485; Fri, 08 Nov 2024 14:39:49 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 8 Nov 2024 14:39:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 8 Nov 2024 14:39:48 +0800 From: Mark Tseng To: "Rafael J . Wysocki" , Viresh Kumar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , Subject: [PATCH v2 1/4] cpufreq: mediatek: CCI support SoC , the transition_delay set to 10 ms Date: Fri, 8 Nov 2024 14:39:39 +0800 Message-ID: <20241108063942.19744-2-chun-jen.tseng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241108063942.19744-1-chun-jen.tseng@mediatek.com> References: <20241108063942.19744-1-chun-jen.tseng@mediatek.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 SoC with CCI architecture should set transition_delay to 10 ms because cpufreq need to call devfreq notifier in async mode. if delay less than 10 ms, it may get wrong OPP-level in devfreq passive governor. Signed-off-by: Mark Tseng --- drivers/cpufreq/mediatek-cpufreq.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 663f61565cf7..f63183154e9a 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -597,6 +597,9 @@ static int mtk_cpufreq_init(struct cpufreq_policy *policy) policy->driver_data = info; policy->clk = info->cpu_clk; + if (info->soc_data->ccifreq_supported) + policy->transition_delay_us = 10000; + return 0; }