| Message ID | 20241119-topic-sm8x50-gpu-bw-vote-v2-4-4deb87be2498@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | drm/msm: adreno: add support for DDR bandwidth scaling via GMU | expand |
On 20/11/2024 12:19, Dmitry Baryshkov wrote: > On Tue, Nov 19, 2024 at 06:56:39PM +0100, Neil Armstrong wrote: >> The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth >> along the Frequency and Power Domain level, but by default we leave the >> OPP core vote for the interconnect ddr path. >> >> While scaling via the interconnect path was sufficient, newer GPUs >> like the A750 requires specific vote paremeters and bandwidth to >> achieve full functionality. >> >> While the feature will require some data in a6xx_info, it's safer >> to only enable tested platforms with this flag first. >> >> Add a new feature enabling DDR Bandwidth vote via GMU. > > Squash into the implementation patch. Which one ? the flag is use in the next 3 patches > >> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >> --- >> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h >> index 4702d4cfca3b58fb3cbb25cb6805f1c19be2ebcb..394b96eb6c83354ae008b15b562bedb96cd391dd 100644 >> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h >> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h >> @@ -58,6 +58,7 @@ enum adreno_family { >> #define ADRENO_FEAT_HAS_HW_APRIV BIT(0) >> #define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(1) >> #define ADRENO_FEAT_PREEMPTION BIT(2) >> +#define ADRENO_FEAT_GMU_BW_VOTE BIT(3) >> >> /* Helper for formating the chip_id in the way that userspace tools like >> * crashdec expect. >> >> -- >> 2.34.1 >> >
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 4702d4cfca3b58fb3cbb25cb6805f1c19be2ebcb..394b96eb6c83354ae008b15b562bedb96cd391dd 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -58,6 +58,7 @@ enum adreno_family { #define ADRENO_FEAT_HAS_HW_APRIV BIT(0) #define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(1) #define ADRENO_FEAT_PREEMPTION BIT(2) +#define ADRENO_FEAT_GMU_BW_VOTE BIT(3) /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect.
The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth along the Frequency and Power Domain level, but by default we leave the OPP core vote for the interconnect ddr path. While scaling via the interconnect path was sufficient, newer GPUs like the A750 requires specific vote paremeters and bandwidth to achieve full functionality. While the feature will require some data in a6xx_info, it's safer to only enable tested platforms with this flag first. Add a new feature enabling DDR Bandwidth vote via GMU. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 1 file changed, 1 insertion(+)