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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF000015CA.mail.protection.outlook.com (10.167.241.200) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8230.7 via Frontend Transport; Sat, 30 Nov 2024 14:07:41 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sat, 30 Nov 2024 08:07:38 -0600 From: Mario Limonciello To: Borislav Petkov CC: Thomas Gleixner , Ingo Molnar , "Dave Hansen" , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . Shenoy" , Mario Limonciello , Perry Yuan , Brijesh Singh , Peter Zijlstra , Li RongQing , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:ACPI" , "open list:AMD PSTATE DRIVER" , Pawan Gupta , Perry Yuan , Bagas Sanjaya Subject: [PATCH v7 01/12] Documentation: x86: Add AMD Hardware Feedback Interface documentation Date: Sat, 30 Nov 2024 08:06:52 -0600 Message-ID: <20241130140703.557-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241130140703.557-1-mario.limonciello@amd.com> References: <20241130140703.557-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CA:EE_|PH8PR12MB6986:EE_ X-MS-Office365-Filtering-Correlation-Id: f988543f-a21f-45c1-3eb8-08dd11485abc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: KjFLqHoU6wUm1vg9Qq9+Vr4dUbVOnlqwleBofnDuCSScl2om3gCi7W9+p6a30FP5pf2hlFW2Rj9H0d17440lWzqHvpwIq2RI6adIfLB0U2A9f5SoDdWf+1MZpl65bElosn6gUTBZKotE8L97OcMtG80KHr15w6bC9LmuLagp6dLql4dZ9KpsBJq2B/UNVzgK/RertVAN6bOU9ZDTDY/uYuoz0sdtKB6SvthJ4wb8SOdrmuzOoS2BNET12Xl3pXSG7AHjMwl4XdAjSC+V4LFfGq86nGAtNhNMCtA/eI+oVlcx0IFKCbcTTLxVqgCFTQ5DmRMFiBIDPl4YCJu9Gz/CQb1rTK2szgREp5rVuSyB1wKOs72KKkM7XCxnVn+0z/gssir/EmXBlhzMy9BxL+pz+gL8lRAka7hlDlVrthKhUFMDIe3UPgsaTnJ00kkxdomSv8JqC0gC39IUtoBG/UXy2ouslqH7nvDv7wktdHNgtDsFbtbk6TPszyGbhuGQQKDB/p8ipvKCXndVU0JtB5skV+HINclfDNHFVaM0q/x/mpmrTSxipwPZisnoDzfgd0MQ7yR85wOUHqYULYHt5bCkkjOqfFvNrOV1BGb/PZN+l79zuwiQnc3Ma+Eyn3oIeUghT6Kj4J6XAKti8euSsd/2DavkcS0/oA3KhSpk79b4/haZ4SaZ44m5qXAH8AJDGnS2YAYTqrycocQDyRCXTjpvCZqdkxrYL6xELqi140BWj8oOKg1IYzhoXTJg6QAgc3vG34Kaei0AqXFKM5EcQFKNkjvfqzcwQb3B1pGYVPXBzqeuBsv6HrgWONGx4XSa/p7mYr1vvBEB85N8yPEjdaJZiaboWxgJqOTnJgMUM91GHfVWHaKFmiXJ60OMCOFzbyPQ2WFycjZJR/YYsi830vwI7NBMGGpnVC6xCkpeIzaE4SbmOSsJ8xsA+ZQFq93Np+Zrf+Sk7rtlYF9vN3H131edZ4ZzmAbU+j0DxQ55gmINPxLo8lrlH2I9wTODCZKA3gjAAV6szpc36StWPfPO25PenT+JiVgeb6hHvmWi6+QCuw7MzyYt9uYmkV9DWNb7pij8jAhNcGjWXeb0L7v6OMa2FHkBHoZQ+pUyaZqSMAU7Q1vzJluJvay4hAkm6cGBY6pZNKaoeQxUMOxRh9GuWSq0JA7Zu6Xb9djmGw3cRH5aqWq6mwTzulf9ZyM2AGAeCOzb4AvA+9OMgGEW39aHp1W8qiZVnsTlBrvzade4o7T3Vzsrezclcaw8kv7T0RVAV8PXdbCP1RHbg8b/wE1NCLR30/bR11qYM0CYFerKipMmyr07gygl1cytFZO9RCeszGoFCSDuapir6r+s68U8/M+gCCNdqV8QKNwq39WRKapBZRi2dwz6zKD71qKGjwdbogpu/0qqPH6FpSTMSzVn/WZh5leruoNrtwMBB3IB/PlxFOZdJvy7VdCLgDxLC/ytbifU X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(7416014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2024 14:07:41.3300 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f988543f-a21f-45c1-3eb8-08dd11485abc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6986 From: Perry Yuan Introduce a new documentation file, `amd_hfi.rst`, which delves into the implementation details of the AMD Hardware Feedback Interface and its associated driver, `amd_hfi`. This documentation describes how the driver provides hint to the OS scheduling which depends on the capability of core performance and efficiency ranking data. This documentation describes * The design of the driver * How the driver provides hints to the OS scheduling * How the driver interfaces with the kernel for efficiency ranking data. Reviewed-by: Bagas Sanjaya Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- Documentation/arch/x86/amd-hfi.rst | 127 +++++++++++++++++++++++++++++ Documentation/arch/x86/index.rst | 1 + 2 files changed, 128 insertions(+) create mode 100644 Documentation/arch/x86/amd-hfi.rst diff --git a/Documentation/arch/x86/amd-hfi.rst b/Documentation/arch/x86/amd-hfi.rst new file mode 100644 index 0000000000000..5d204688470e3 --- /dev/null +++ b/Documentation/arch/x86/amd-hfi.rst @@ -0,0 +1,127 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================================================== +Hardware Feedback Interface For Hetero Core Scheduling On AMD Platform +====================================================================== + +:Copyright: 2024 Advanced Micro Devices, Inc. All Rights Reserved. + +:Author: Perry Yuan +:Author: Mario Limonciello + +Overview +-------- + +AMD Heterogeneous Core implementations are comprised of more than one +architectural class and CPUs are comprised of cores of various efficiency and +power capabilities: performance-oriented *classic cores* and power-efficient +*dense cores*. As such, power management strategies must be designed to +accommodate the complexities introduced by incorporating different core types. +Heterogeneous systems can also extend to more than two architectural classes as +well. The purpose of the scheduling feedback mechanism is to provide +information to the operating system scheduler in real time such that the +scheduler can direct threads to the optimal core. + +The goal of AMD's heterogeneous architecture is to attain power benefit by sending +background thread to the dense cores while sending high priority threads to the classic +cores. From a performance perspective, sending background threads to dense cores can free +up power headroom and allow the classic cores to optimally service demanding threads. +Furthermore, the area optimized nature of the dense cores allows for an increasing +number of physical cores. This improved core density will have positive multithreaded +performance impact. + +AMD Heterogeneous Core Driver +----------------------------- + +The ``amd_hfi`` driver delivers the operating system a performance and energy efficiency +capability data for each CPU in the system. The scheduler can use the ranking data +from the HFI driver to make task placement decisions. + +Thread Classification and Ranking Table Interaction +---------------------------------------------------- + +The thread classification is used to select into a ranking table that describes +an efficiency and performance ranking for each classification. + +Threads are classified during runtime into enumerated classes. The classes represent +thread performance/power characteristics that may benefit from special scheduling behaviors. +The below table depicts an example of thread classification and a preference where a given thread +should be scheduled based on its thread class. The real time thread classification is consumed +by the operating system and is used to inform the scheduler of where the thread should be placed. + +Thread Classification Example Table +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ++----------+----------------+-------------------------------+---------------------+---------+ +| class ID | Classification | Preferred scheduling behavior | Preemption priority | Counter | ++----------+----------------+-------------------------------+---------------------+---------+ +| 0 | Default | Performant | Highest | | ++----------+----------------+-------------------------------+---------------------+---------+ +| 1 | Non-scalable | Efficient | Lowest | PMCx1A1 | ++----------+----------------+-------------------------------+---------------------+---------+ +| 2 | I/O bound | Efficient | Lowest | PMCx044 | ++----------+----------------+-------------------------------+---------------------+---------+ + +Thread classification is performed by the hardware each time that the thread is switched out. +Threads that don't meet any hardware specified criteria will be classified as "default". + +AMD Hardware Feedback Interface +-------------------------------- + +The Hardware Feedback Interface provides to the operating system information +about the performance and energy efficiency of each CPU in the system. Each +capability is given as a unit-less quantity in the range [0-255]. A higher +performance value indicates higher performance capability, and a higher +efficiency value indicates more efficiency. Energy efficiency and performance +are reported in separate capabilities in the shared memory based ranking table. + +These capabilities may change at runtime as a result of changes in the +operating conditions of the system or the action of external factors. +Power Management FW is responsible for detecting events that would require +a reordering of the performance and efficiency ranking. Table updates would +happen relatively infrequently and occur on the time scale of seconds or more. + +The following events trigger a table update: + * Thermal Stress Events + * Silent Compute + * Extreme Low Battery Scenarios + +The kernel or a userspace policy daemon can use these capabilities to modify +task placement decisions. For instance, if either the performance or energy +capabilities of a given logical processor becomes zero, it is an indication that +the hardware recommends to the operating system to not schedule any tasks on +that processor for performance or energy efficiency reasons, respectively. + +Implementation details for Linux +-------------------------------- + +The implementation of threads scheduling consists of the following steps: + +1. A thread is spawned and scheduled to the ideal core using the default + heterogeneous scheduling policy. +2. The processor profiles thread execution and assigns an enumerated classification ID. + This classification is communicated to the OS via logical processor scope MSR. +3. During the thread context switch out the operating system consumes the workload(WL) + classification which resides in a logical processor scope MSR. +4. The OS triggers the hardware to clear its history by writing to an MSR, + after consuming the WL classification and before switching in the new thread. +5. If due to the classification, ranking table, and processor availability, + the thread is not on its ideal processor, the OS will then consider scheduling + the thread on its ideal processor (if available). + +Ranking Table +------------- +The ranking table is a shared memory region that is used to communicate the +performance and energy efficiency capabilities of each CPU in the system. + +The ranking table design includes rankings for each APIC ID in the system and +rankings both for performance and efficiency for each workload classification. + +.. kernel-doc:: drivers/platform/x86/amd/hfi/hfi.c + :doc: amd_shmem_info + +Ranking Table update +--------------------------- +The power management firmware issues an platform interrupt after updating the ranking +table and is ready for the operating system to consume it. CPUs receive such interrupt +and read new ranking table from shared memory which PCCT table has provided, then +``amd_hfi`` driver parse the new table to provide new consume data for scheduling decisions. diff --git a/Documentation/arch/x86/index.rst b/Documentation/arch/x86/index.rst index 8ac64d7de4dc9..56f2923f52597 100644 --- a/Documentation/arch/x86/index.rst +++ b/Documentation/arch/x86/index.rst @@ -43,3 +43,4 @@ x86-specific Documentation features elf_auxvec xstate + amd-hfi