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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v7 03/12] x86/msr-index: define AMD heterogeneous CPU related MSR Date: Sat, 30 Nov 2024 09:20:14 -0600 Message-ID: <20241130152023.684-4-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241130152023.684-1-mario.limonciello@amd.com> References: <20241130152023.684-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37B:EE_|SA1PR12MB6846:EE_ X-MS-Office365-Filtering-Correlation-Id: f082e2d3-017e-4195-3f48-08dd11529216 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: sNBdIoPcPK2GImYl4Sc9ikgDi0Z0tdZIvRcYZordPWwyQ0X0YqM1e2Kw0f8aKnyL/x6Mpoxd/KvKbTzsFcqW9lvyjkicDmu9ZUc33ylb6bbrO5dmaf45YzMpOqqjQCpC/QArfmR6nPtCMHWBkpjJNSp144WE9Y5qNwwE5ekTiir84fm0cgDoh9oKcngFdTqI7/uVhYh3rDBb2OM8vSg/A4KZeKg1cLJGouIBXF7eEwFpJUa+Q/mPyFhZ8Iy7GVv3OnX8g98J/mBRkNWjWW8pF4M1qAZ7d/qJ8Cay77VIXX/uf7G/VEW8vUBw1hdW8IVEzNewzwiRGxa+uqfJRJ7eZeLuUzYS3s8SHx9RGOrfar8LxdGyYS+BGkepK3Zqn4gyEiaIRufdzE8H1gI89vGkb2BY3Q+bsCEy0T0UaiER+5jWCAGaNdidAyPclU+9c8JNnfNa8pkIdxZCpjEzmCI3anLSOtJHHm/CY0G/71326u8apk+dzazGeBm9Ei4+ufGVOuHbEeRl01JEF3VQ8P2cTdKHhUqQck2Tixwh26ox8cStI8pMvmVctIAFJt7zVM4+S/qRxAEeYwuS1vPziHTArgjgsI1yupoTUjB79x1ACkRJ6MinvbC3b42AZ+ttk1/wCDLTvo1eHhdcdnpusEPfVsSuyEL+lboSxmz8l7DxqCSq1zF1NbjRiMfnZKGr24OpErvUxQVNF1SHxAWf90bjA8/x1jm7ecrXimodL02UO7EaeLOr7VEG2iPelrBCswVpGlQY6JERDDAsT7+Ab9VIRWYvVucA8DnCoos5ZM+LGZk+OSYZ4j4iupG2EDa5B3WcRs0yIZtLAbtfPJgIgpNzf8ZDFZYNKyvtlRgjyVrQOcRiy+DG00GGc9JUmw9PeemY9NWI/0Ss/LKaMwunc468bUK/qhY299dySzOlg+0eTpVHANZ66/7URnqUvxkrzs6NcbWLKBCo8//0gYJi0DB//t8B/igjrKWUOZ9fvCJBF1pjPWmiReDyih26ITseLvgPkE7sqinOhpCd16lUzDm8qoDPqvSsyvqwLL0OZBpEbgclh5g9lxRsiSoLFbwON1vhcO0VjSaFDgTUep/PFK6w6brBTg2sGqsL+qgxCHO0vKCF28Fmw1jOHgI33mOTpeQYEDXgdhPGBGv/9MGtxCHpwDNIBssTyIMQ/aojy3qQJzbYtZ3GbakJNFqgkdk3lNIILZojp0OTnzbklvPQgoFrw5pJTkwrdlz5JIzZpru0YSFwqt1bS2ZcvzcR5cwtP/JTpnS0y4djuCALRn6ZyvfA2F9S42DCnS/rDX7D3vkjmzSAXRX8x4OYs4eES/YiYxg6gN1laUcmUdTD7jkWsTLbZGYmFgzDnhEO2UH7y+oq7LZdnNpiR8/o3i6RPTv5Vi/L5C2NPGJQH1MuVYwAKNQhGXz2bAFbFZj/k+tIP4RdsyTOvXrkYC3UE9I73pX0GK06 X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2024 15:20:49.1306 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f082e2d3-017e-4195-3f48-08dd11529216 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6846 From: Perry Yuan Introduces new MSR registers for AMD hardware feedback support. These registers enable the system to provide workload classification and configuration capabilities. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 3ae84c3b8e6db..0cd5ffe50f4a4 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -712,6 +712,11 @@ #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 +/* AMD Hardware Feedback Support MSRs */ +#define AMD_WORKLOAD_CLASS_CONFIG 0xc0000500 +#define AMD_WORKLOAD_CLASS_ID 0xc0000501 +#define AMD_WORKLOAD_HRST 0xc0000502 + /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e