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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH v3 06/15] cpufreq/amd-pstate: Use FIELD_PREP and FIELD_GET macros Date: Mon, 9 Dec 2024 12:52:39 -0600 Message-ID: <20241209185248.16301-7-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241209185248.16301-1-mario.limonciello@amd.com> References: <20241209185248.16301-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A34B:EE_|MN2PR12MB4206:EE_ X-MS-Office365-Filtering-Correlation-Id: 4f648dd5-64a8-4643-e50c-08dd1882bc80 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: iCyS5wPrWaG9+eOMWoD2cNntstkWO5xBElNMiCG0N40YUTbLfmiJpQzbr7Ysl81DTOijjpaxXExnwbpo9TyCR5dD7SyvKQ78GZ1WN4jpgRNt+7GpBnA9ZMvifneYW2ZNEc0nHe77WDqPjjrpsg8+2LFrVox+Bry3M0jG8cMUKsUwtP3y4vYxjn5IEF+gdnlHQByULnGrCIdrQlBvM7Gm0d2nBrK74ZNnsin4+DXr3e75apCaa79Y71WHt9eGgXOCbdcVdA5IUE3/q26dWFMwYbZoWELr14pJdE+Q7mtsijkYAqmR6lHpJJCZAB6O0V75gLempIfk12ut0FyoUlqKD9uIW52pciIE6FJCSdltDg3lKzZ3EK/Mi73qwdW32IqNodjehKFPs/kCWpWTB7W7Rn96wAmnZR8s8WBoRcAhHeJpdRQmd+7QRU1Jr4eiXs9keESPR+9nSw3YGp8pk/OMI+z5w/EzqArcm668g6sFKOInInJMAGWR5hEYKU8U6osxAnVIDdcHRbgIYkIUAVJx/MRMjDsPXOe0c2IoIjsnBdGKGF2+E4u1U5obUg2xkkMTD/nFZnG4ei0bfudv3gKTlNWplWe1RM6Rk8j+H1jxl1AzAE4ogevL50hXC2FgqHj4WgofKDpR1YOm3uP4n2HzqGCkyTT/E4R9c6/uciQDfi/pz6i/z5Ra3y8JjWT2UBQeJbq3EScuMgH+U6CkxaXH9AyiXywBWIKcKU18uVNe1En2ioFKwM8PRzb8D4jMQpaUyfXFMSTqP5lG731C/XoGQXNYhwjOqFOz/hWyzhpnchvgWMEwG15my7K6FFyD/t48Ja0KshWHEE9HqOQiwgiHClD4yXEV6kTmA5OdQXkZxb9R3F2qN1hvWrXxKUQPRqdvFlmKh9fJ0uWaTTsFKuHFCzB4ZUZDsqB9ufPNo2S38Pv3uJYsMybIXBp4JWQDoX4H1hJ6wjCAkqGFOG0noXrp4Ug0px5jAUQo+3bJaRvr6+FjE+Vsu6skQTCyru6uOU+AZGYq/tzYEwrB/Maw/Z5LUArC01gqrQs11HAsCfbbcV6PzWc0NIwUBR5Uo4f3OMXhiAvlCFUl8UJfZJhhsH5kNE6ft4why+pkqLDlvNQPY9N/bJI6b4DmYWkrtxZR0/FERxqLNGp7INFJTZSt0zx0Tl19eHWneYlmTg/j31TxMUJ/j2NVagMD4A02yxDFUgjMOvZZstgEik7QPfb+ZOwMfbtsm3NNk+RBf/DsWMYcB6Gms9I6nLDFnyNvolRmS85ZOV7ILBNULY1IEij9aY0gw++et39ZdHP5GsONCgG9gC//z1hEJPLJudO0BFU/7TPs5fogKqfjCTTScgcolYsssfm2xOIRfYp39iZBW1B1jcCb7Xaz8RfR/MO5cZY8efjQldQjLK+Zib42Yj92uVIC9KFIKx9IvRAvXv+V/Tnoq0QiOzJwvFs69UEWNJyO08rt X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2024 18:53:14.2919 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f648dd5-64a8-4643-e50c-08dd1882bc80 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4206 The FIELD_PREP and FIELD_GET macros improve readability and help to avoid shifting bugs. Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- v2: * Add a missing case to traces * Use AMD_CPPC instead of AMD_PSTATE --- drivers/cpufreq/amd-pstate.c | 51 ++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index dd25e7e615984..0ed04316a8d80 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -22,6 +22,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include #include #include #include @@ -88,6 +89,11 @@ static bool cppc_enabled; static bool amd_pstate_prefcore = true; static struct quirk_entry *quirks; +#define AMD_CPPC_MAX_PERF_MASK GENMASK(7, 0) +#define AMD_CPPC_MIN_PERF_MASK GENMASK(15, 8) +#define AMD_CPPC_DES_PERF_MASK GENMASK(23, 16) +#define AMD_CPPC_EPP_PERF_MASK GENMASK(31, 24) + /* * AMD Energy Preference Performance (EPP) * The EPP is used in the CCLK DPM controller to drive @@ -182,7 +188,6 @@ static DEFINE_MUTEX(amd_pstate_driver_lock); static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) { - u64 epp; int ret; if (!cppc_req_cached) { @@ -192,9 +197,8 @@ static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) return ret; } } - epp = (cppc_req_cached >> 24) & 0xFF; - return (s16)epp; + return FIELD_GET(AMD_CPPC_EPP_PERF_MASK, cppc_req_cached); } DEFINE_STATIC_CALL(amd_pstate_get_epp, msr_get_epp); @@ -269,12 +273,11 @@ static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata, static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp) { - int ret; - u64 value = READ_ONCE(cpudata->cppc_req_cached); + int ret; - value &= ~GENMASK_ULL(31, 24); - value |= (u64)epp << 24; + value &= ~AMD_CPPC_EPP_PERF_MASK; + value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); WRITE_ONCE(cpudata->cppc_req_cached, value); ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); @@ -327,8 +330,8 @@ static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata, if (trace_amd_pstate_epp_perf_enabled()) { trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, epp, - AMD_CPPC_MIN_PERF(cpudata->cppc_req_cached), - AMD_CPPC_MAX_PERF(cpudata->cppc_req_cached), + FIELD_GET(AMD_CPPC_MIN_PERF_MASK, cpudata->cppc_req_cached), + FIELD_GET(AMD_CPPC_MAX_PERF_MASK, cpudata->cppc_req_cached), cpudata->boost_state); } @@ -542,18 +545,15 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, des_perf = 0; } - value &= ~AMD_CPPC_MIN_PERF(~0L); - value |= AMD_CPPC_MIN_PERF(min_perf); - - value &= ~AMD_CPPC_DES_PERF(~0L); - value |= AMD_CPPC_DES_PERF(des_perf); - /* limit the max perf when core performance boost feature is disabled */ if (!cpudata->boost_supported) max_perf = min_t(unsigned long, nominal_perf, max_perf); - value &= ~AMD_CPPC_MAX_PERF(~0L); - value |= AMD_CPPC_MAX_PERF(max_perf); + value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | + AMD_CPPC_DES_PERF_MASK); + value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); + value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf); + value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) { trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq, @@ -1573,16 +1573,11 @@ static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) min_perf = min(cpudata->nominal_perf, max_perf); - /* Initial min/max values for CPPC Performance Controls Register */ - value &= ~AMD_CPPC_MIN_PERF(~0L); - value |= AMD_CPPC_MIN_PERF(min_perf); - - value &= ~AMD_CPPC_MAX_PERF(~0L); - value |= AMD_CPPC_MAX_PERF(max_perf); - - /* CPPC EPP feature require to set zero to the desire perf bit */ - value &= ~AMD_CPPC_DES_PERF(~0L); - value |= AMD_CPPC_DES_PERF(0); + value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | + AMD_CPPC_DES_PERF_MASK); + value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); + value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, 0); + value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); /* Get BIOS pre-defined epp value */ epp = amd_pstate_get_epp(cpudata, value); @@ -1652,7 +1647,7 @@ static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) if (trace_amd_pstate_epp_perf_enabled()) { trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, cpudata->epp_cached, - AMD_CPPC_MIN_PERF(cpudata->cppc_req_cached), + FIELD_GET(AMD_CPPC_MIN_PERF_MASK, cpudata->cppc_req_cached), max_perf, cpudata->boost_state); }