From patchwork Fri Apr 4 02:59:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 878375 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E81B8149E17; Fri, 4 Apr 2025 02:59:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735584; cv=none; b=bsPWlCa/qHC/QpeGh/7dNnrara+DWPat5CgysTEbrvu4HdOFZPOx7ciXrVIGKuwJHPA+ukdv43obWLorZM3t9wp1W5sMNHp8qsJ0rxZSiuvAtW4nHTpITBsXh2VtVA11G3V4IaiyqwtPvxQ0z7ikhcg1lDD44H1W/Q1McadeqDc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743735584; c=relaxed/simple; bh=BFNG9yNPBQp7lePtcF6xD0SGvnVh48+ACatG3ueW7Nc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ndkbzm/yf17XGrYIrf/jhMl/aKBzHGI9U9B6bA+Ac8JT21uQi1TPcXK+lMBXDeaGZ6GE9nIraxkglIzDc4HYT9XfeUo6TWkBbehiDiZfkc3/6rOfMlzG025xll8xN3QEJBvo+xdZY6A7EIXHVegleRuLr86OCsNNbeOrKz3OlHM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VJ0e7SAx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VJ0e7SAx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0DBB4C4CEF9; Fri, 4 Apr 2025 02:59:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743735583; bh=BFNG9yNPBQp7lePtcF6xD0SGvnVh48+ACatG3ueW7Nc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=VJ0e7SAxLo+dcCqV1y3fiUbeOj8nzMsubkIcSK61bhYmhFqk2usnd0d5OPi7EKFdM DRyI+aUiub90+OB8O8n9WkGNHSq5XjDhMNm+jODyHcVHCh8hI7SogIEa2XHIKBVbw8 6tHA5u923suAWQtSIIk/r+qK55kVswhMUDnDMPy8x6G2h1iJ6myNUFghF4bIy9SHk7 1uL3lBV9f3bS0qy+RIFP3V8Bnxf3aItkKniTAn6Dhy/J/vRlG5X3AfYwDnSpkSqKXZ 5Fe4SyAA72tc2gCFbxbhmwKehbH+Di1xzgWfn9O8OHHZMPggV0LnlKOpky195Gw6O8 kIqHaQHcEPOZg== From: "Rob Herring (Arm)" Date: Thu, 03 Apr 2025 21:59:23 -0500 Subject: [PATCH 02/19] arm64: dts: broadcom: bcm2712: Use "l2-cache" for L2 cache node names Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250403-dt-cpu-schema-v1-2-076be7171a85@kernel.org> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> In-Reply-To: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> To: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Bjorn Andersson , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , zhouyanjie@wanyeetech.com, Conor Dooley , Nicolas Ferre , Claudiu Beznea , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-rockchip@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-renesas-soc@vger.kernel.org X-Mailer: b4 0.15-dev There's no need include the CPU number in the L2 cache node names as the names are local to the CPU nodes. The documented node name is also just "l2-cache". Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index 9e610a89a337..ad0cac8e4444 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -64,7 +64,7 @@ cpu0: cpu@0 { i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l0>; - l2_cache_l0: l2-cache-l0 { + l2_cache_l0: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; @@ -88,7 +88,7 @@ cpu1: cpu@1 { i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l1>; - l2_cache_l1: l2-cache-l1 { + l2_cache_l1: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; @@ -112,7 +112,7 @@ cpu2: cpu@2 { i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l2>; - l2_cache_l2: l2-cache-l2 { + l2_cache_l2: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>; @@ -136,7 +136,7 @@ cpu3: cpu@3 { i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set next-level-cache = <&l2_cache_l3>; - l2_cache_l3: l2-cache-l3 { + l2_cache_l3: l2-cache { compatible = "cache"; cache-size = <0x80000>; cache-line-size = <64>;