From patchwork Mon Apr 14 21:41:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 881165 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AD1A1F8731; Mon, 14 Apr 2025 21:42:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666931; cv=none; b=WcjDS5qziYd6+QNpgoeAHwQjf/lLwgDKjfcpBugRcdkL1gcyRyVGRKe3W9wWoqewJVh9KpS1hiv4GOfaB1eOwPa0HfbUEGzh1D91y1WkPajhFK2gTV60Y/QsQrLRknw2brgLq5hHhQ+PM/ReV3wKR/5ZGIYgaP35TTL+368GImo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744666931; c=relaxed/simple; bh=jUvxnIYUbRoDsGcxWrRs5hQT0rBrN7ve+6frDdnr+zc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kPLocxjqmMtvbkhMReKiJngIKpOK9FfE/rdALqBZkhVCdqDMysEqH4MAha3bNJrb0Y+SczXgt8C6UTNm6GJmAg8Ko3tSaMXH8HQqD6pA4QwYXSeQoS2qtS0PAweV22ibrAXpAattepz5Fnae4xc7aV9lir8fPxKGJieD9DKkym0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ha8m4C6s; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ha8m4C6s" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1744666929; x=1776202929; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jUvxnIYUbRoDsGcxWrRs5hQT0rBrN7ve+6frDdnr+zc=; b=ha8m4C6s5biXrefQBRKl5Nts4CsgH3jENSXRudq2JtNmCy3WX/C3LFL4 4oYJ7nfrOv4og6jVz8nEM/kgCHBaucGEN/dsQD6BPemD2jqGPYt7jtqpP 1l+Fb+I9Azs5uamm9ceDv6aM0bc6pJlLo2HEQv+8G8kLNAVXlwHd8BMjB 1/lkV7VGbe/FekqmYbWP1kpnQipDY/hEP8Og7vpbjy1N/LjOV/xGZN7hr 7wGhn1dUEucNXOU+EbWqvai98exvex51NibjPHiUmKm+tiU4tgVJVSe4o 1R2+S9Af/cRdgZZs3nGSES+DiXf3KRE3Sfyf6MV2SiWOaItsN2ZfbS7/M Q==; X-CSE-ConnectionGUID: jf75aQsXSneWELgtntpGWQ== X-CSE-MsgGUID: H+TRc6fwTnGuExqarZ3BvA== X-IronPort-AV: E=Sophos;i="6.15,212,1739862000"; d="scan'208";a="40006677" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 14 Apr 2025 14:41:57 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 14 Apr 2025 14:41:06 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 14 Apr 2025 14:41:06 -0700 From: To: , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v5 09/11] ARM: dts: microchip: sama7d65: Add SRAM and DRAM components support Date: Mon, 14 Apr 2025 14:41:26 -0700 Message-ID: <354ecd628fdd292d2125570a6b10a93cbecb7706.1744666011.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Add SRAM, secumod, UDDRC, and DDR3phy to enable support for low power modes. Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index b6710ccd4c36..8439c6a9e9f2 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -47,6 +47,14 @@ slow_xtal: clock-slowxtal { }; }; + ns_sram: sram@100000 { + compatible = "mmio-sram"; + reg = <0x100000 0x20000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + }; + soc { compatible = "simple-bus"; ranges; @@ -58,6 +66,23 @@ sfrbu: sfr@e0008000 { reg = <0xe0008000 0x20>; }; + securam: sram@e0000800 { + compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram"; + reg = <0xe0000800 0x4000>; + ranges = <0 0xe0000800 0x4000>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; + #address-cells = <1>; + #size-cells = <1>; + no-memory-wc; + }; + + secumod: security-module@e0004000 { + compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon"; + reg = <0xe0004000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + }; + pioa: pinctrl@e0014000 { compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"; reg = <0xe0014000 0x800>; @@ -227,6 +252,16 @@ i2c10: i2c@600 { }; }; + uddrc: uddrc@e3800000 { + compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc"; + reg = <0xe3800000 0x4000>; + }; + + ddr3phy: ddr3phy@e3804000 { + compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy"; + reg = <0xe3804000 0x1000>; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,cortex-a7-gic"; reg = <0xe8c11000 0x1000>,