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[209.132.180.67]) by mx.google.com with ESMTP id i16si2382524pgv.496.2017.12.06.11.45.05; Wed, 06 Dec 2017 11:45:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-rt-users-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=DoP3Ra9J; spf=pass (google.com: best guess record for domain of linux-rt-users-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-rt-users-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752312AbdLFTpE (ORCPT + 4 others); Wed, 6 Dec 2017 14:45:04 -0500 Received: from mail-wr0-f196.google.com ([209.85.128.196]:44378 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752362AbdLFTov (ORCPT ); Wed, 6 Dec 2017 14:44:51 -0500 Received: by mail-wr0-f196.google.com with SMTP id l22so5101661wrc.11 for ; Wed, 06 Dec 2017 11:44:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BL7MNGsFJHzh9iuhaPLwnIKlO2L0viHJHw1NaMe/+d0=; b=DoP3Ra9JcaGQyn2jVGzl+u90f/z3fxxRBRqkoe1OQIliGygn6N47xYs4qLmqEiDqui lp4ITXWEI3skiSyHBVRvKZaIfDokk83Bw/rB4mBsQPxU1gJ62DiBVscsZN+MjhslndE1 7IDzIKzp/lMN+ZuSy3Q3FQ1bGNoIO+f6mYwkc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BL7MNGsFJHzh9iuhaPLwnIKlO2L0viHJHw1NaMe/+d0=; b=NYqv0yWokAKwY7hU+ahpcG1/g8HeT+E1ztc4jbVGmzYeo3RId8XlyXm6/gtjnr8tiP 4vhOfLImew+VuX7hZr1Vl5n/KDmMyJuuWK4R4bhLUnwf5Zd+iAw9yMRNw6qU1rZO527G dvVbImIBegmcyUf9OULRFq2V0Y5KeT+JzO+ezPMMk1CAmyAR3YeLUzJmeSXi2aAbHRhT 1SnoEeuyNCr29BadKyX7593GXv2KwdWpkryC7VR5SX8DLW3CJ8U2v189UdLHZVSUrdx7 dZmogyB8YptHeQogm5t66PrahyPCRmGxX7W/47OoVU/LIpQxULFp3vvZdE2zwQGrheXQ hj7A== X-Gm-Message-State: AJaThX69XE3OUmibMyneaCOOSFCki2E80BViNThPqT45F5AW7GZFvl0A 2PG8aYbwRfSicPxFQNwX4dOLYQ== X-Received: by 10.223.176.27 with SMTP id f27mr21352453wra.105.1512589490251; Wed, 06 Dec 2017 11:44:50 -0800 (PST) Received: from localhost.localdomain ([105.150.171.234]) by smtp.gmail.com with ESMTPSA id b66sm3596594wmh.32.2017.12.06.11.44.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Dec 2017 11:44:49 -0800 (PST) From: Ard Biesheuvel To: linux-crypto@vger.kernel.org Cc: herbert@gondor.apana.org.au, linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Dave Martin , Russell King - ARM Linux , Sebastian Andrzej Siewior , Mark Rutland , linux-rt-users@vger.kernel.org, Peter Zijlstra , Catalin Marinas , Will Deacon , Steven Rostedt , Thomas Gleixner Subject: [PATCH v3 18/20] crypto: arm64/crc32-ce - yield NEON after every block of input Date: Wed, 6 Dec 2017 19:43:44 +0000 Message-Id: <20171206194346.24393-19-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171206194346.24393-1-ard.biesheuvel@linaro.org> References: <20171206194346.24393-1-ard.biesheuvel@linaro.org> Sender: linux-rt-users-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rt-users@vger.kernel.org Avoid excessive scheduling delays under a preemptible kernel by yielding the NEON after every block of input. Signed-off-by: Ard Biesheuvel --- arch/arm64/crypto/crc32-ce-core.S | 44 ++++++++++++++------ 1 file changed, 32 insertions(+), 12 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe linux-rt-users" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/crypto/crc32-ce-core.S b/arch/arm64/crypto/crc32-ce-core.S index 18f5a8442276..b4ddbb2027e5 100644 --- a/arch/arm64/crypto/crc32-ce-core.S +++ b/arch/arm64/crypto/crc32-ce-core.S @@ -100,9 +100,9 @@ dCONSTANT .req d0 qCONSTANT .req q0 - BUF .req x0 - LEN .req x1 - CRC .req x2 + BUF .req x19 + LEN .req x20 + CRC .req x21 vzr .req v9 @@ -116,13 +116,21 @@ * size_t len, uint crc32) */ ENTRY(crc32_pmull_le) - adr x3, .Lcrc32_constants + frame_push 4, 64 + + adr x22, .Lcrc32_constants b 0f ENTRY(crc32c_pmull_le) - adr x3, .Lcrc32c_constants + frame_push 4, 64 + + adr x22, .Lcrc32c_constants + +0: mov BUF, x0 + mov LEN, x1 + mov CRC, x2 -0: bic LEN, LEN, #15 + bic LEN, LEN, #15 ld1 {v1.16b-v4.16b}, [BUF], #0x40 movi vzr.16b, #0 fmov dCONSTANT, CRC @@ -131,7 +139,7 @@ ENTRY(crc32c_pmull_le) cmp LEN, #0x40 b.lt less_64 - ldr qCONSTANT, [x3] + ldr qCONSTANT, [x22] loop_64: /* 64 bytes Full cache line folding */ sub LEN, LEN, #0x40 @@ -161,10 +169,21 @@ loop_64: /* 64 bytes Full cache line folding */ eor v4.16b, v4.16b, v8.16b cmp LEN, #0x40 - b.ge loop_64 + b.lt less_64 + + if_will_cond_yield_neon + stp q1, q2, [sp, #48] + stp q3, q4, [sp, #80] + do_cond_yield_neon + ldp q1, q2, [sp, #48] + ldp q3, q4, [sp, #80] + ldr qCONSTANT, [x22] + movi vzr.16b, #0 + endif_yield_neon + b loop_64 less_64: /* Folding cache line into 128bit */ - ldr qCONSTANT, [x3, #16] + ldr qCONSTANT, [x22, #16] pmull2 v5.1q, v1.2d, vCONSTANT.2d pmull v1.1q, v1.1d, vCONSTANT.1d @@ -203,8 +222,8 @@ fold_64: eor v1.16b, v1.16b, v2.16b /* final 32-bit fold */ - ldr dCONSTANT, [x3, #32] - ldr d3, [x3, #40] + ldr dCONSTANT, [x22, #32] + ldr d3, [x22, #40] ext v2.16b, v1.16b, vzr.16b, #4 and v1.16b, v1.16b, v3.16b @@ -212,7 +231,7 @@ fold_64: eor v1.16b, v1.16b, v2.16b /* Finish up with the bit-reversed barrett reduction 64 ==> 32 bits */ - ldr qCONSTANT, [x3, #48] + ldr qCONSTANT, [x22, #48] and v2.16b, v1.16b, v3.16b ext v2.16b, vzr.16b, v2.16b, #8 @@ -222,6 +241,7 @@ fold_64: eor v1.16b, v1.16b, v2.16b mov w0, v1.s[1] + frame_pop 4, 64 ret ENDPROC(crc32_pmull_le) ENDPROC(crc32c_pmull_le)