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[209.132.180.67]) by mx.google.com with ESMTP id 1si21002472plu.508.2017.12.26.02.33.13; Tue, 26 Dec 2017 02:33:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-rt-users-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=BjU7sszT; spf=pass (google.com: best guess record for domain of linux-rt-users-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-rt-users-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751266AbdLZKbR (ORCPT + 4 others); Tue, 26 Dec 2017 05:31:17 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:43136 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750953AbdLZKbO (ORCPT ); Tue, 26 Dec 2017 05:31:14 -0500 Received: by mail-wm0-f66.google.com with SMTP id n138so34457612wmg.2 for ; Tue, 26 Dec 2017 02:31:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5FJvE4TZ320kLEjn0IS/ezWe6M00vG4Z7O6NEpxxNho=; b=BjU7sszTVXY7ZfNvErY2zDoWRHKt2LXjK5oC6RZdj1wb3mvmY6QqI/YshtRLtB/ZAe 0AZtHdfEt48Te5JreRC9qdFFiSatBdID00ctauBp70DNVdXGtp8ztNtXUlY3LuXpcsm9 2auXzFoktLJBCOQeVXk7tndEQ8zeJuhMD537U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5FJvE4TZ320kLEjn0IS/ezWe6M00vG4Z7O6NEpxxNho=; b=ryup/3UsCmaH5MqG9eTnku/jsPaTnNzbwDUPoWsoOYSgPIUooPwnoRmR6vjZAe0wjy Nimwom9Go8Bg5uZxSJi3PIL4qYqOCTy70OZ1ogjFV4X9FBqZu7kS+0+4BVKOrkU8edRw 587k/hSSRCqwyXYI2JSOkxdgIVI04vQu3VJRCmZayTv6nBfCvMKvkXZ7iTn+uucNM3Ti DzJznl8VsxmPV9erLqD9s46dLwHMqIBfcJ56Lwbm5MPXpjuKwING8MJHQDnf6cslvXRs 0CJ+j8uAtN/F6sUVYZKyE57xxJMyi8q4wVZkf5tPvi0pd0Upm0aAjlW/zUzuokAmwWZ4 ViBQ== X-Gm-Message-State: AKGB3mK+soGsiONL4oinRDETEOd9pTokteKcIHF6AHEJEOT/Hh/fc54J mHClOTOxZLl5OFXvIFxQ8qBQfw== X-Received: by 10.28.107.211 with SMTP id a80mr19974960wmi.71.1514284273287; Tue, 26 Dec 2017 02:31:13 -0800 (PST) Received: from localhost.localdomain ([160.171.216.245]) by smtp.gmail.com with ESMTPSA id l142sm13974036wmb.43.2017.12.26.02.31.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Dec 2017 02:31:12 -0800 (PST) From: Ard Biesheuvel To: linux-kernel@vger.kernel.org Cc: Ard Biesheuvel , Dave Martin , Russell King - ARM Linux , Sebastian Andrzej Siewior , Mark Rutland , linux-rt-users@vger.kernel.org, Peter Zijlstra , Catalin Marinas , Will Deacon , Steven Rostedt , Thomas Gleixner Subject: [PATCH v4 12/20] crypto: arm64/sha1-ce - yield NEON after every block of input Date: Tue, 26 Dec 2017 10:29:32 +0000 Message-Id: <20171226102940.26908-13-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171226102940.26908-1-ard.biesheuvel@linaro.org> References: <20171226102940.26908-1-ard.biesheuvel@linaro.org> Sender: linux-rt-users-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rt-users@vger.kernel.org Avoid excessive scheduling delays under a preemptible kernel by yielding the NEON after every block of input. Signed-off-by: Ard Biesheuvel --- arch/arm64/crypto/sha1-ce-core.S | 42 ++++++++++++++------ 1 file changed, 29 insertions(+), 13 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe linux-rt-users" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/crypto/sha1-ce-core.S b/arch/arm64/crypto/sha1-ce-core.S index 8550408735a0..ded039415f4f 100644 --- a/arch/arm64/crypto/sha1-ce-core.S +++ b/arch/arm64/crypto/sha1-ce-core.S @@ -70,31 +70,37 @@ * int blocks) */ ENTRY(sha1_ce_transform) + frame_push 3 + + mov x19, x0 + mov x20, x1 + mov x21, x2 + /* load round constants */ - adr x6, .Lsha1_rcon +0: adr x6, .Lsha1_rcon ld1r {k0.4s}, [x6], #4 ld1r {k1.4s}, [x6], #4 ld1r {k2.4s}, [x6], #4 ld1r {k3.4s}, [x6] /* load state */ - ld1 {dgav.4s}, [x0] - ldr dgb, [x0, #16] + ld1 {dgav.4s}, [x19] + ldr dgb, [x19, #16] /* load sha1_ce_state::finalize */ ldr_l w4, sha1_ce_offsetof_finalize, x4 - ldr w4, [x0, x4] + ldr w4, [x19, x4] /* load input */ -0: ld1 {v8.4s-v11.4s}, [x1], #64 - sub w2, w2, #1 +1: ld1 {v8.4s-v11.4s}, [x20], #64 + sub w21, w21, #1 CPU_LE( rev32 v8.16b, v8.16b ) CPU_LE( rev32 v9.16b, v9.16b ) CPU_LE( rev32 v10.16b, v10.16b ) CPU_LE( rev32 v11.16b, v11.16b ) -1: add t0.4s, v8.4s, k0.4s +2: add t0.4s, v8.4s, k0.4s mov dg0v.16b, dgav.16b add_update c, ev, k0, 8, 9, 10, 11, dgb @@ -125,16 +131,25 @@ CPU_LE( rev32 v11.16b, v11.16b ) add dgbv.2s, dgbv.2s, dg1v.2s add dgav.4s, dgav.4s, dg0v.4s - cbnz w2, 0b + cbz w21, 3f + + if_will_cond_yield_neon + st1 {dgav.4s}, [x19] + str dgb, [x19, #16] + do_cond_yield_neon + b 0b + endif_yield_neon + + b 1b /* * Final block: add padding and total bit count. * Skip if the input size was not a round multiple of the block size, * the padding is handled by the C code in that case. */ - cbz x4, 3f +3: cbz x4, 4f ldr_l w4, sha1_ce_offsetof_count, x4 - ldr x4, [x0, x4] + ldr x4, [x19, x4] movi v9.2d, #0 mov x8, #0x80000000 movi v10.2d, #0 @@ -143,10 +158,11 @@ CPU_LE( rev32 v11.16b, v11.16b ) mov x4, #0 mov v11.d[0], xzr mov v11.d[1], x7 - b 1b + b 2b /* store new state */ -3: st1 {dgav.4s}, [x0] - str dgb, [x0, #16] +4: st1 {dgav.4s}, [x19] + str dgb, [x19, #16] + frame_pop ret ENDPROC(sha1_ce_transform)