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Fri, 5 Jul 2024 02:11:14 +0000 (GMT) Received: from epsmgmcp1.samsung.com (unknown [182.195.42.82]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20240705021114epsmtrp1d5f56136fe83724be89c56b94f50ffc4~fLzIRgZ1z0593405934epsmtrp1M; Fri, 5 Jul 2024 02:11:14 +0000 (GMT) X-AuditID: b6c32a4d-001ff700000262f0-70-668756430b18 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgmcp1.samsung.com (Symantec Messaging Gateway) with SMTP id 60.0A.18846.24657866; Fri, 5 Jul 2024 11:11:14 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.60]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20240705021114epsmtip250ab3cb5d6404e669af930df6f667712~fLzIFGkWO0030900309epsmtip2j; Fri, 5 Jul 2024 02:11:14 +0000 (GMT) From: Sunyeal Hong To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Sunyeal Hong Subject: [PATCH 0/5] initial clock support for exynosauto v920 SoC Date: Fri, 5 Jul 2024 11:11:05 +0900 Message-ID: <20240705021110.2495344-1-sunyeal.hong@samsung.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupkk+LIzCtJLcpLzFFi42LZdljTVNc5rD3NYM1RdosH87axWVz/8pzV 4vz5DewWH3vusVpc3jWHzWLG+X1MFhdPuVocftPOavHv2kYWi6Zl65kcuDze32hl99i0qpPN o2/LKkaPz5vkAliism0yUhNTUosUUvOS81My89JtlbyD453jTc0MDHUNLS3MlRTyEnNTbZVc fAJ03TJzgO5RUihLzCkFCgUkFhcr6dvZFOWXlqQqZOQXl9gqpRak5BSYF+gVJ+YWl+al6+Wl llgZGhgYmQIVJmRnPDtWU7CNq2L1zE9sDYyzOboYOTkkBEwkPnauYe1i5OIQEtjDKDHvzR52 COcTo0TrqW5WkCow5/oMMZiO403XGSGKdjJKXLx5kwXC+cgoce1aM3MXIwcHm4CuxJ9/DiBx EYHvjBL9b/eBFTELdDJKXD26nQlklLCAk8SPMwvYQGwWAVWJB8ems4A08wrYS6x/XAexTV7i 4prnYCW8AoISJ2c+YQGxmYHizVtnM4PMlBC4xS6x/8oXsMUSAi4Ss85FQfQKS7w6voUdwpaS eNnfBmXnS0y+/pYJorcB6Oh/3cwQCXuJRWd+soPMYRbQlFi/Sx9ipLLEkVtQa/kkOg7/ZYcI 80p0tAlBNKpJfLpyGWqIjMSxE8+gjvGQePc+CRKEsRLHnk5gncAoPwvJL7OQ/DILYe0CRuZV jFKpBcW56anJRgWGunmp5fBYTc7P3cQITpNavjsYX6//q3eIkYmD8RCjBAezkgiv1PvmNCHe lMTKqtSi/Pii0pzU4kOMpsAAnsgsJZqcD0zUeSXxhiaWBiZmZobmRqYG5krivPda56YICaQn lqRmp6YWpBbB9DFxcEo1MC2ZOf+/FnOs9ooNS+y6Mo1jv9pU5TBwTT9q9z8o0/jEpbjDv5RT H9wOee/JHzz536lpx9QqP19ZPe+gRMjEniOcuv9kX0wv2tKW6H2PQ1ypWXk5R9/bTWtVWb2f /HkVOmfiiZe1XMUZX7kS3v886jPFXczzSCjz+QtSItx67yu/1n7heCg+Wf/A59lGWnV6d96k nj5vxHvP68yaP22zL5lY1K5hNZ6fKfkq/aLs3QPTPm1zP+opr2ZzbFVS4RGVWt5nUYJqgUki kW86Oq5vjJEo0Wi+/K2ZlUtiZURlfVfnPk1v07ibIafkTjJVBlxbIM7NP//Rm1aJR9yPN5q+ 0IyfdWR7tefak91Nf9qOuSuxFGckGmoxFxUnAgD3enlnHAQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrMLMWRmVeSWpSXmKPExsWy7bCSvK5TWHuaQc9ETYsH87axWVz/8pzV 4vz5DewWH3vusVpc3jWHzWLG+X1MFhdPuVocftPOavHv2kYWi6Zl65kcuDze32hl99i0qpPN o2/LKkaPz5vkAliiuGxSUnMyy1KL9O0SuDKeHasp2MZVsXrmJ7YGxtkcXYycHBICJhLHm64z djFycQgJbGeUmLX2ADtEQkZiY8N/KFtY4n7LEVaIoveMEjeuXWDpYuTgYBPQlfjzzwEkLiLw m1Hix97vYJOYBXoZJe7c/scE0i0s4CTx48wCNhCbRUBV4sGx6WDNvAL2Eusf10EskJe4uOY5 WAmvgKDEyZlPWEBsZqB489bZzBMY+WYhSc1CklrAyLSKUTS1oDg3PTe5wFCvODG3uDQvXS85 P3cTIzhctYJ2MC5b/1fvECMTB+MhRgkOZiURXqn3zWlCvCmJlVWpRfnxRaU5qcWHGKU5WJTE eZVzOlOEBNITS1KzU1MLUotgskwcnFINTGmrVIpdX6XzB5ZJtGxfq+mhY73ZZUK/pC8/S6v6 8h9XpvD0/du29qxc+P2oE0ps0mHfe6tmm725FVy8M5dj/1+t5IK8qQ2ft0fc337U6f+tim+c azSFM+dO3L/Q++P7DBuGlc/EtjD9uG04RWz3tLXV1x2CPh8UeSH1cr8wx0fLL7dMyxSS7WqC WPTC5n6ar9b78Ypa0oIXaTEHvJ/JsH1Z/a1Dx/J4gv7hyXn5/DfeezyRPvMyo/4z98eJOasv aT7fxc8TL/nR9IBX4fTpHcmTf6ybWK0yueHa+71HWH3knSY0m8c8WSvNpdHKxJkbr3fMtT3w fNmphWeMwxhUfk28+uv3pbmdhz96uAWnCyixFGckGmoxFxUnAgD7k0RGxgIAAA== X-CMS-MailID: 20240705021114epcas2p4bad9380e73d2681aabc6074905e112ab X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240705021114epcas2p4bad9380e73d2681aabc6074905e112ab References: This patchset adds initial clock driver support for Exynos Auto v920 SoC. This driver uses HW Auto Clock gating. So all gate clocks did not register. Below CMU blocks are supported in this patchset and remains will be implemented later. - CMU_TOP - CMU_PERIC0 Sunyeal Hong (5): dt-bindings: clock: add Exynos Auto v920 SoC CMU bindings dt-bindings: clock: add clock binding definitions for Exynos Auto v920 arm64: dts: exynos: add initial CMU clock nodes in Exynos Auto v920 clk: samsung: clk-pll: Add support for pll_531x clk: samsung: add top clock support for Exynos Auto v920 SoC .../clock/samsung,exynosautov920-clock.yaml | 115 ++ .../arm64/boot/dts/exynos/exynosautov920.dtsi | 40 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynosautov920.c | 1176 +++++++++++++++++ drivers/clk/samsung/clk-pll.c | 45 + drivers/clk/samsung/clk-pll.h | 1 + .../clock/samsung,exynosautov920.h | 191 +++ 7 files changed, 1556 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml create mode 100644 drivers/clk/samsung/clk-exynosautov920.c create mode 100644 include/dt-bindings/clock/samsung,exynosautov920.h