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[v2,0/4] initial clock support for exynosauto v920 SoC

Message ID 20240707231331.3433340-1-sunyeal.hong@samsung.com
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Series initial clock support for exynosauto v920 SoC | expand

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Sunyeal Hong July 7, 2024, 11:13 p.m. UTC 
This patchset adds initial clock driver support for Exynos Auto v920 SoC.
This driver uses HW Auto Clock gating. So all gate clocks did not register.

Below CMU blocks are supported in this patchset and remains will be
implemented later.

- CMU_TOP
- CMU_PERIC0

Changes in v2:
 - Fix typo from v209 to v920
 - Change USI clock to appropriate
 - Merge headers into binding patches
 - Change clock-name to the recommended name

Sunyeal Hong (4):
  dt-bindings: clock: add Exynos Auto v920 SoC CMU bindings
  arm64: dts: exynos: add initial CMU clock nodes in Exynos Auto v920
  clk: samsung: clk-pll: Add support for pll_531x
  clk: samsung: add top clock support for Exynos Auto v920 SoC

 .../clock/samsung,exynosautov920-clock.yaml   |  115 ++
 .../arm64/boot/dts/exynos/exynosautov920.dtsi |   40 +-
 drivers/clk/samsung/Makefile                  |    1 +
 drivers/clk/samsung/clk-exynosautov920.c      | 1173 +++++++++++++++++
 drivers/clk/samsung/clk-pll.c                 |   45 +
 drivers/clk/samsung/clk-pll.h                 |    1 +
 .../clock/samsung,exynosautov920.h            |  191 +++
 7 files changed, 1553 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
 create mode 100644 drivers/clk/samsung/clk-exynosautov920.c
 create mode 100644 include/dt-bindings/clock/samsung,exynosautov920.h

Comments

Alim Akhtar July 8, 2024, 11:05 a.m. UTC | #1 
> -----Original Message-----
> From: Sunyeal Hong <sunyeal.hong@samsung.com>
> Sent: Monday, July 8, 2024 4:43 AM
> To: Krzysztof Kozlowski <krzk@kernel.org>; Sylwester Nawrocki
> <s.nawrocki@samsung.com>; Chanwoo Choi <cw00.choi@samsung.com>;
> Alim Akhtar <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob
> Herring <robh@kernel.org>; Conor Dooley <conor+dt@kernel.org>
> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; Sunyeal Hong <sunyeal.hong@samsung.com>
> Subject: [PATCH v2 2/4] arm64: dts: exynos: add initial CMU clock nodes in
> Exynos Auto v920
> 
> Add cmu_top, cmu_peric0 clock nodes and
> switch USI clocks instead of dummy fixed-rate-clock.
> 
> Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com>
> ---
>  .../arm64/boot/dts/exynos/exynosautov920.dtsi | 40 +++++++++++++------
>  1 file changed, 27 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> index c1c8566d74f5..54fc32074379 100644
> --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> @@ -6,6 +6,7 @@
>   *
>   */
> 
> +#include <dt-bindings/clock/samsung,exynosautov920.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/soc/samsung,exynos-usi.h>
> 
> @@ -38,17 +39,6 @@ xtcxo: clock {
>  		clock-output-names = "oscclk";
>  	};
> 
> -	/*
> -	 * FIXME: Keep the stub clock for serial driver, until proper clock
> -	 * driver is implemented.
> -	 */
> -	clock_usi: clock-usi {
> -		compatible = "fixed-clock";
> -		#clock-cells = <0>;
> -		clock-frequency = <200000000>;
> -		clock-output-names = "usi";
> -	};
> -
>  	cpus: cpus {
>  		#address-cells = <2>;
>  		#size-cells = <0>;
> @@ -182,6 +172,28 @@ chipid@10000000 {
>  			reg = <0x10000000 0x24>;
>  		};
> 
> +		cmu_peric0: clock-controller@10800000 {
> +			compatible = "samsung,exynosautov920-cmu-
> peric0";
> +			reg = <0x10800000 0x8000>;
Please cross check the size of the register range, this looks to be more then what is needed. 

> +			#clock-cells = <1>;
> +
> +			clocks = <&xtcxo>,
> +				 <&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
> +				 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
> +			clock-names = "oscclk",
> +				      "noc",
> +				      "ip";
> +		};
> +
> +		cmu_top: clock-controller@11000000 {
> +			compatible = "samsung,exynosautov920-cmu-top";
> +			reg = <0x11000000 0x8000>;
> +			#clock-cells = <1>;
> +
> +			clocks = <&xtcxo>;
> +			clock-names = "oscclk";
> +		};
> +
>  		gic: interrupt-controller@10400000 {
>  			compatible = "arm,gic-v3";
>  			#interrupt-cells = <3>;
> @@ -213,7 +225,8 @@ usi_0: usi@108800c0 {
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges;
> -			clocks = <&clock_usi>, <&clock_usi>;
> +			clocks = <&cmu_peric0
> CLK_MOUT_PERIC0_NOC_USER>,
> +				 <&cmu_peric0
> CLK_DOUT_PERIC0_USI00_USI>;
>  			clock-names = "pclk", "ipclk";
>  			status = "disabled";
> 
> @@ -224,7 +237,8 @@ serial_0: serial@10880000 {
>  				interrupts = <GIC_SPI 764
> IRQ_TYPE_LEVEL_HIGH>;
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&uart0_bus>;
> -				clocks = <&clock_usi>, <&clock_usi>;
> +				clocks = <&cmu_peric0
> CLK_MOUT_PERIC0_NOC_USER>,
> +					 <&cmu_peric0
> CLK_DOUT_PERIC0_USI00_USI>;
>  				clock-names = "uart", "clk_uart_baud0";
>  				samsung,uart-fifosize = <256>;
>  				status = "disabled";
> --
> 2.45.2