From patchwork Tue Nov 22 09:35:30 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Daniel Kachhap X-Patchwork-Id: 5271 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C852023E10 for ; Tue, 22 Nov 2011 09:38:21 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id BC2FDA186DA for ; Tue, 22 Nov 2011 09:38:21 +0000 (UTC) Received: by faaa26 with SMTP id a26so209820faa.11 for ; Tue, 22 Nov 2011 01:38:21 -0800 (PST) Received: by 10.152.111.170 with SMTP id ij10mr8150532lab.5.1321954701474; Tue, 22 Nov 2011 01:38:21 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.41.198 with SMTP id h6cs169507lal; Tue, 22 Nov 2011 01:38:21 -0800 (PST) Received: by 10.236.191.198 with SMTP id g46mr24997360yhn.118.1321954699396; Tue, 22 Nov 2011 01:38:19 -0800 (PST) Received: from mail-gx0-f178.google.com (mail-gx0-f178.google.com [209.85.161.178]) by mx.google.com with ESMTPS id x21si3680105ybx.109.2011.11.22.01.38.18 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 22 Nov 2011 01:38:19 -0800 (PST) Received-SPF: pass (google.com: domain of amitdanielk@gmail.com designates 209.85.161.178 as permitted sender) client-ip=209.85.161.178; Authentication-Results: mx.google.com; spf=pass (google.com: domain of amitdanielk@gmail.com designates 209.85.161.178 as permitted sender) smtp.mail=amitdanielk@gmail.com; dkim=pass (test mode) header.i=@gmail.com Received: by mail-gx0-f178.google.com with SMTP id k4so6621707ggn.37 for ; Tue, 22 Nov 2011 01:38:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=rDYA4B3a41+jWFDmk/UCJkY9wl69LiFNNzFBZ8344Fw=; b=r6L+Xz7wqk73qD4YkU9wU2rPMfU9ji4Q5AKdIyGwXJ1STunFvk24I8qbWuaOpyIBrF cdbnw+pXupS7W2E/zVpWfqZUiMcAenxyvIT0o7JGkhuLNrtx8zLD2+641JAvHS7F2E7g qzqlG+a63RjXq5bb7LX3jvZPIETblkYa+fbHs= Received: by 10.50.77.229 with SMTP id v5mr19241896igw.13.1321954698394; Tue, 22 Nov 2011 01:38:18 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id el2sm10208537ibb.10.2011.11.22.01.38.13 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 22 Nov 2011 01:38:18 -0800 (PST) Sender: amit kachhap From: Amit Daniel Kachhap To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, amit.kachhap@linaro.org, patches@linaro.org Subject: [PATCH V3 4/6] ARM: s5p: add L2 early resume code Date: Tue, 22 Nov 2011 15:05:30 +0530 Message-Id: <1321954532-18724-5-git-send-email-amit.kachhap@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1321954532-18724-1-git-send-email-amit.kachhap@linaro.org> References: <1321954532-18724-1-git-send-email-amit.kachhap@linaro.org> This patch adds code to resume L2 before MMU is enabled in suspend and cpuidle resume paths. Signed-off-by: Lorenzo Pieralisi Signed-off-by: Amit Daniel Kachhap --- arch/arm/plat-s5p/sleep.S | 28 ++++++++++++++++++++++++++++ 1 files changed, 28 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-s5p/sleep.S b/arch/arm/plat-s5p/sleep.S index c371ba2..40bd9bf 100644 --- a/arch/arm/plat-s5p/sleep.S +++ b/arch/arm/plat-s5p/sleep.S @@ -23,6 +23,8 @@ */ #include +#include +#include .text @@ -47,5 +49,31 @@ .data ENTRY(s3c_cpu_resume) +#ifdef CONFIG_CACHE_L2X0 + adr r0, l2x0_regs_phys + ldr r0, [r0] + ldr r1, [r0, #L2X0_R_PHY_BASE] + ldr r2, [r1, #L2X0_CTRL] + tst r2, #0x1 + bne resume_l2on + ldr r2, [r0, #L2X0_R_AUX_CTRL] + str r2, [r1, #L2X0_AUX_CTRL] + ldr r2, [r0, #L2X0_R_TAG_LATENCY] + str r2, [r1, #L2X0_TAG_LATENCY_CTRL] + ldr r2, [r0, #L2X0_R_DATA_LATENCY] + str r2, [r1, #L2X0_DATA_LATENCY_CTRL] + ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] + str r2, [r1, #L2X0_PREFETCH_CTRL] + ldr r2, [r0, #L2X0_R_PWR_CTRL] + str r2, [r1, #L2X0_POWER_CTRL] + mov r2, #1 + str r2, [r1, #L2X0_CTRL] +resume_l2on: +#endif b cpu_resume ENDPROC(s3c_cpu_resume) +#ifdef CONFIG_CACHE_L2X0 + .globl l2x0_regs_phys +l2x0_regs_phys: + .long 0 +#endif