From patchwork Tue Nov 22 09:35:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Daniel Kachhap X-Patchwork-Id: 5272 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 6B02323E10 for ; Tue, 22 Nov 2011 09:38:28 +0000 (UTC) Received: from mail-gx0-f180.google.com (mail-gx0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id 3ACF1A186DA for ; Tue, 22 Nov 2011 09:38:28 +0000 (UTC) Received: by mail-gx0-f180.google.com with SMTP id v5so7919414ggn.11 for ; Tue, 22 Nov 2011 01:38:28 -0800 (PST) Received: by 10.152.162.10 with SMTP id xw10mr11241952lab.12.1321954707458; Tue, 22 Nov 2011 01:38:27 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.41.198 with SMTP id h6cs169511lal; Tue, 22 Nov 2011 01:38:27 -0800 (PST) Received: by 10.50.160.161 with SMTP id xl1mr19351366igb.5.1321954705317; Tue, 22 Nov 2011 01:38:25 -0800 (PST) Received: from mail-iy0-f178.google.com (mail-iy0-f178.google.com [209.85.210.178]) by mx.google.com with ESMTPS id hs6si2907954ibb.124.2011.11.22.01.38.24 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 22 Nov 2011 01:38:25 -0800 (PST) Received-SPF: pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.178 as permitted sender) client-ip=209.85.210.178; Authentication-Results: mx.google.com; spf=pass (google.com: domain of amitdanielk@gmail.com designates 209.85.210.178 as permitted sender) smtp.mail=amitdanielk@gmail.com; dkim=pass (test mode) header.i=@gmail.com Received: by iadj38 with SMTP id j38so10301536iad.37 for ; Tue, 22 Nov 2011 01:38:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=Q39EuHxvrhSurnbJF6+hfr/+TzqPSmEbbDs98PqykLk=; b=ZNRHECSN3WOlJvJWZ1tzYUTMzo+he5TVIXMEeEzNySz5RigKyyZUR9eMfCodxo6Bza N9+r/NeVvSgJ0/4W6+AShF0cNp6FQa1eYS+trLUDEtcdY75ZmngwLPkAO7eUZ+1qJC1L 1Jpz9owFPHTIbE0kXG2tJnDcmty1wsLif/oac= Received: by 10.231.67.141 with SMTP id r13mr3655139ibi.98.1321954704541; Tue, 22 Nov 2011 01:38:24 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id el2sm10208537ibb.10.2011.11.22.01.38.18 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 22 Nov 2011 01:38:24 -0800 (PST) Sender: amit kachhap From: Amit Daniel Kachhap To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, amit.kachhap@linaro.org, patches@linaro.org Subject: [PATCH V3 5/6] ARM: exynos: remove useless code to save/restore L2 Date: Tue, 22 Nov 2011 15:05:31 +0530 Message-Id: <1321954532-18724-6-git-send-email-amit.kachhap@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1321954532-18724-1-git-send-email-amit.kachhap@linaro.org> References: <1321954532-18724-1-git-send-email-amit.kachhap@linaro.org> Following the merge of CPU PM notifiers and L2 resume code, this patch removes useless code to save and restore L2 registers. This is now automatically covered by suspend calls which integrated CPU PM notifiers and new sleep code that allows to resume L2 before MMU is turned on. Signed-off-by: Lorenzo Pieralisi Signed-off-by: Amit Daniel Kachhap --- arch/arm/mach-exynos/pm.c | 15 --------------- 1 files changed, 0 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 4093fea..1883cc9 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -155,13 +155,6 @@ static struct sleep_save exynos4_core_save[] = { SAVE_ITEM(S5P_SROM_BC3), }; -static struct sleep_save exynos4_l2cc_save[] = { - SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), -}; /* For Cortex-A9 Diagnostic and Power control register */ static unsigned int save_arm_register[2]; @@ -182,7 +175,6 @@ static void exynos4_pm_prepare(void) u32 tmp; s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); - s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); @@ -384,13 +376,6 @@ static void exynos4_pm_resume(void) scu_enable(S5P_VA_SCU); -#ifdef CONFIG_CACHE_L2X0 - s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); - outer_inv_all(); - /* enable L2X0*/ - writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); -#endif - early_wakeup: return; }