From patchwork Tue Feb 21 04:33:26 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: thomas.abraham@linaro.org X-Patchwork-Id: 6849 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id E127223E01 for ; Tue, 21 Feb 2012 04:27:23 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id A94AFA18586 for ; Tue, 21 Feb 2012 04:27:23 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id z7so11793389iab.11 for ; Mon, 20 Feb 2012 20:27:23 -0800 (PST) Received: from mr.google.com ([10.50.135.37]) by 10.50.135.37 with SMTP id pp5mr17023527igb.26.1329798443535 (num_hops = 1); Mon, 20 Feb 2012 20:27:23 -0800 (PST) MIME-Version: 1.0 Received: by 10.50.135.37 with SMTP id pp5mr13743336igb.26.1329798443478; Mon, 20 Feb 2012 20:27:23 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.11.10 with SMTP id r10csp75180ibr; Mon, 20 Feb 2012 20:27:23 -0800 (PST) Received: by 10.68.220.168 with SMTP id px8mr14979219pbc.123.1329798442782; Mon, 20 Feb 2012 20:27:22 -0800 (PST) Received: from mailout4.samsung.com (mailout4.samsung.com. [203.254.224.34]) by mx.google.com with ESMTP id g9si22737982pbd.311.2012.02.20.20.27.22; Mon, 20 Feb 2012 20:27:22 -0800 (PST) Received-SPF: neutral (google.com: 203.254.224.34 is neither permitted nor denied by best guess record for domain of thomas.abraham@linaro.org) client-ip=203.254.224.34; Authentication-Results: mx.google.com; spf=neutral (google.com: 203.254.224.34 is neither permitted nor denied by best guess record for domain of thomas.abraham@linaro.org) smtp.mail=thomas.abraham@linaro.org Received: from epcpsbgm1.samsung.com (mailout4.samsung.com [203.254.224.34]) by mailout4.samsung.com (Oracle Communications Messaging Exchange Server 7u4-19.01 64bit (built Sep 7 2010)) with ESMTP id <0LZQ00GYD70NI350@mailout4.samsung.com> for patches@linaro.org; Tue, 21 Feb 2012 13:27:05 +0900 (KST) X-AuditID: cbfee61a-b7b78ae000001ceb-2c-4f431d195b3c Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (MMPCPMTA) with SMTP id 1A.24.07403.91D134F4; Tue, 21 Feb 2012 13:27:05 +0900 (KST) Received: from localhost.localdomain ([107.108.73.37]) by mmp1.samsung.com (Oracle Communications Messaging Exchange Server 7u4-19.01 64bit (built Sep 7 2010)) with ESMTPA id <0LZQ009HB70R0J20@mmp1.samsung.com> for patches@linaro.org; Tue, 21 Feb 2012 13:27:05 +0900 (KST) From: Thomas Abraham To: linux-samsung-soc@vger.kernel.org Cc: rob.herring@calxeda.com, grant.likely@secretlab.ca, kgene.kim@samsung.com, linux-arm-kernel@lists.infradead.org, patches@linaro.org Subject: [PATCH v4 2/2] ARM: Exynos: Add device tree support for interrupt combiner Date: Tue, 21 Feb 2012 10:03:26 +0530 Message-id: <1329798806-32482-3-git-send-email-thomas.abraham@linaro.org> X-Mailer: git-send-email 1.6.6.rc2 In-reply-to: <1329798806-32482-1-git-send-email-thomas.abraham@linaro.org> References: <1329798806-32482-1-git-send-email-thomas.abraham@linaro.org> X-Brightmail-Tracker: AAAAAA== X-Gm-Message-State: ALoCoQkMeEOLazSSKbEToIiOBXhB2Ws8myadcm74vXy0DuVcyNy/CayOdOAPkSY5t8Ryu4kz9ZKt Add device tree based instantiation of the interrupt combiner controller. Cc: Grant Likely Cc: Rob Herring Signed-off-by: Thomas Abraham Acked-by: Grant Likely --- .../bindings/arm/samsung/interrupt-combiner.txt | 48 ++++++++++++++++++ arch/arm/mach-exynos/common.c | 53 ++++++++++++++++++- 2 files changed, 98 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt diff --git a/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt new file mode 100644 index 0000000..2a57211 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt @@ -0,0 +1,48 @@ +* Samsung Exynos Interrupt Combiner Controller + +Samsung's Exynos4 architecture includes a interrupt combiner controller which +can combine interrupt sources as a group and provide a single interrupt request +for the group. The interrupt request from each group are connected to a parent +interrupt controller, such as GIC in case of Exynos4210. + +The interrupt combiner controller consists of multiple combiners. Upto eight +interrupt sources can be connected to a combiner. The combiner outputs one +combined interrupt for its eight interrupt sources. The combined interrupt +is usually connected to a parent interrupt controller. + +A single node in the device tree is used to describe the interrupt combiner +controller module (which includes multiple combiners). A combiner in the +interrupt controller module shares config/control registers with other +combiners. For example, a 32-bit interrupt enable/disable config register +can accommodate upto 4 interrupt combiners (with each combiner supporting +upto 8 interrupt sources). + +Required properties: +- compatible: should be "samsung,exynos4210-combiner". +- interrupt-controller: Identifies the node as an interrupt controller. +- #interrupt-cells: should be <2>. The meaning of the cells are + * First Cell: Combiner Group Number. + * Second Cell: Interrupt number within the group. +- reg: Base address and size of interrupt combiner registers. +- interrupts: The list of interrupts generated by the combiners which are then + connected to a parent interrupt controller. The format of the interrupt + specifier depends in the interrupt parent controller. + +Optional properties: +- interrupt-parent: pHandle of the parent interrupt controller, if not + inherited from the parent node. + +Example: + + The following is a an example from the Exynos4210 SoC dtsi file. + + combiner:interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x10440000 0x1000>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; + }; diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 0c06fa6..ac5ac0e 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -372,6 +373,30 @@ static void __init combiner_init_one(unsigned int combiner_nr, base + COMBINER_ENABLE_CLEAR); } +#ifdef CONFIG_OF +static int combiner_irq_domain_xlate(struct irq_domain *d, + struct device_node *controller, const u32 *intspec, + unsigned int intsize, unsigned long *out_hwirq, + unsigned int *out_type) +{ + if (d->of_node != controller) + return -EINVAL; + if (intsize < 2) + return -EINVAL; + *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1]; + *out_type = 0; + return 0; +} +#else +static int combiner_irq_domain_xlate(struct irq_domain *d, + struct device_node *controller, const u32 *intspec, + unsigned int intsize, unsigned long *out_hwirq, + unsigned int *out_type) +{ + return -EINVAL; +} +#endif + static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { @@ -382,12 +407,13 @@ static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq, } static struct irq_domain_ops combiner_irq_domain_ops = { + .xlate = combiner_irq_domain_xlate, .map = combiner_irq_domain_map, }; void __init combiner_init(void __iomem *combiner_base, struct device_node *np) { - int i, irq_base; + int i, irq, irq_base; int nr_irq = MAX_COMBINER_NR * MAX_IRQ_IN_COMBINER; irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0); @@ -406,13 +432,33 @@ void __init combiner_init(void __iomem *combiner_base, struct device_node *np) for (i = 0; i < MAX_COMBINER_NR; i++) { combiner_init_one(i, combiner_base + (i >> 2) * 0x10); - combiner_cascade_irq(i, IRQ_SPI(i)); +#ifdef CONFIG_OF + irq = np ? irq_of_parse_and_map(np, i) : IRQ_SPI(i); +#else + irq = IRQ_SPI(i); +#endif + combiner_cascade_irq(i, irq); } } #ifdef CONFIG_OF +void __init combiner_of_init(struct device_node *np, struct device_node *parent) +{ + void __iomem *combiner_base; + + combiner_base = of_iomap(np, 0); + if (!combiner_base) { + pr_err("combiner_of_init: failed to map combiner registers\n"); + return; + } + + combiner_init(combiner_base, np); +} + static const struct of_device_id exynos4_dt_irq_match[] = { { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, + { .compatible = "samsung,exynos4210-combiner", + .data = combiner_of_init, }, {}, }; #endif @@ -430,7 +476,8 @@ void __init exynos4_init_irq(void) of_irq_init(exynos4_dt_irq_match); #endif - combiner_init(S5P_VA_COMBINER_BASE, NULL); + if (!of_have_populated_dt()) + combiner_init(S5P_VA_COMBINER_BASE, NULL); /* * The parameters of s5p_init_irq() are for VIC init.