From patchwork Wed Aug 28 13:39:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikas C Sajjan X-Patchwork-Id: 19562 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ve0-f199.google.com (mail-ve0-f199.google.com [209.85.128.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 8FEF3248D3 for ; Wed, 28 Aug 2013 13:40:20 +0000 (UTC) Received: by mail-ve0-f199.google.com with SMTP id m1sf6888792ves.2 for ; Wed, 28 Aug 2013 06:40:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=MzKxfxbtY0pzdU1jzzYgnHM1QdHAPu1aZ4I8dfl9WT0=; b=mqpvxhOR4wiHXI0ocJ1h2YQjPR7E3K1T2cRd/2IoEZqNVIerMNOEOvr/Xy5hSO1aiX mYL44qrEZuzF+EZR7d43ctauENOU1p3niZu9Fq85AkhB/wj7Bo/YtvKIBMd13lvl4uYY 0Wsdb3YI2vOeTYSVSiZ00VaLuYE5fXmJjLhsmzbj/GeR7555Q+2lr7e7N5wrkO8qonho e6RLzJR5sAIkegsowNjOtDABvPIZiLxV9jY98zsSQTyx87R0Cw+GtliBcMqxGR1GByVx xAPkZzLS8GZe18lH2UpPH+8AhXy9GYYQziii/cnv6+Gj/22IPtXXkiBVMfUC3w/AHIpq Z82A== X-Received: by 10.236.115.198 with SMTP id e46mr10699019yhh.33.1377697220254; Wed, 28 Aug 2013 06:40:20 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.128.133 with SMTP id no5ls347996qeb.2.gmail; Wed, 28 Aug 2013 06:40:20 -0700 (PDT) X-Received: by 10.58.118.130 with SMTP id km2mr25442590veb.0.1377697220103; Wed, 28 Aug 2013 06:40:20 -0700 (PDT) Received: from mail-vb0-f46.google.com (mail-vb0-f46.google.com [209.85.212.46]) by mx.google.com with ESMTPS id jf10si6526065vdb.24.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 28 Aug 2013 06:40:20 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.212.46 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.46; Received: by mail-vb0-f46.google.com with SMTP id p13so4110512vbe.33 for ; Wed, 28 Aug 2013 06:40:20 -0700 (PDT) X-Gm-Message-State: ALoCoQld0XivGhDxy1UvPgJykcPMbiP6szN0ABSLHRDw2sp/9ezkdIhP/9L/RPD/6nRQAl6E2FxB X-Received: by 10.52.88.115 with SMTP id bf19mr1474196vdb.12.1377697219999; Wed, 28 Aug 2013 06:40:19 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp356455vcz; Wed, 28 Aug 2013 06:40:19 -0700 (PDT) X-Received: by 10.68.160.5 with SMTP id xg5mr15123753pbb.173.1377697218980; Wed, 28 Aug 2013 06:40:18 -0700 (PDT) Received: from mail-pa0-f54.google.com (mail-pa0-f54.google.com [209.85.220.54]) by mx.google.com with ESMTPS id fa1si481864pab.303.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 28 Aug 2013 06:40:18 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.54 is neither permitted nor denied by best guess record for domain of vikas.sajjan@linaro.org) client-ip=209.85.220.54; Received: by mail-pa0-f54.google.com with SMTP id kx10so6259199pab.41 for ; Wed, 28 Aug 2013 06:40:18 -0700 (PDT) X-Received: by 10.68.171.193 with SMTP id aw1mr2320006pbc.197.1377697218405; Wed, 28 Aug 2013 06:40:18 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id fk4sm33976049pab.23.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 28 Aug 2013 06:40:17 -0700 (PDT) From: Vikas Sajjan To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, t.figa@samsung.com, mturquette@linaro.org, patches@linaro.org, linaro-kernel@lists.linaro.org, joshi@samsung.com Subject: [PATCH v2 2/2] clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC Date: Wed, 28 Aug 2013 19:09:58 +0530 Message-Id: <1377697198-19097-3-git-send-email-vikas.sajjan@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1377697198-19097-1-git-send-email-vikas.sajjan@linaro.org> References: <1377697198-19097-1-git-send-email-vikas.sajjan@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: vikas.sajjan@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.46 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Adds APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC. Signed-off-by: Vikas Sajjan --- drivers/clk/samsung/clk-exynos5420.c | 78 ++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index e035fd0..5cbe313 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -757,6 +757,76 @@ static struct of_device_id ext_clk_match[] __initdata = { { }, }; +static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(2000000000, 250, 3, 0), + PLL_35XX_RATE(1900000000, 475, 6, 0), + PLL_35XX_RATE(1800000000, 225, 3, 0), + PLL_35XX_RATE(1700000000, 425, 6, 0), + PLL_35XX_RATE(1600000000, 200, 3, 0), + PLL_35XX_RATE(1500000000, 250, 4, 0), + PLL_35XX_RATE(1400000000, 175, 3, 0), + PLL_35XX_RATE(1300000000, 325, 6, 0), + PLL_35XX_RATE(1200000000, 200, 2, 1), + PLL_35XX_RATE(1100000000, 275, 3, 1), + PLL_35XX_RATE(1000000000, 250, 3, 1), + PLL_35XX_RATE(900000000, 150, 2, 1), + PLL_35XX_RATE(800000000, 200, 3, 1), + PLL_35XX_RATE(700000000, 175, 3, 1), + PLL_35XX_RATE(600000000, 200, 2, 2), + PLL_35XX_RATE(500000000, 250, 3, 2), + PLL_35XX_RATE(400000000, 200, 3, 2), + PLL_35XX_RATE(300000000, 400, 4, 3), + PLL_35XX_RATE(200000000, 200, 3, 3), + { }, +}; + +static struct samsung_pll_rate_table kpll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(1300000000, 325, 6, 0), + PLL_35XX_RATE(1200000000, 200, 2, 1), + PLL_35XX_RATE(1100000000, 275, 3, 1), + PLL_35XX_RATE(1000000000, 250, 3, 1), + PLL_35XX_RATE(900000000, 150, 2, 1), + PLL_35XX_RATE(800000000, 200, 3, 1), + PLL_35XX_RATE(700000000, 175, 3, 1), + PLL_35XX_RATE(600000000, 200, 2, 2), + PLL_35XX_RATE(500000000, 250, 3, 2), + PLL_35XX_RATE(400000000, 200, 3, 2), + PLL_35XX_RATE(300000000, 400, 4, 3), + PLL_35XX_RATE(200000000, 200, 3, 3), + { }, +}; + +static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_36XX_RATE(rate, m, p, s, k) */ + PLL_36XX_RATE(192000000, 64, 2, 2, 0), + PLL_36XX_RATE(180633605, 45, 3, 1, 10381), + PLL_36XX_RATE(180000000, 45, 3, 1, 0), + PLL_36XX_RATE(73728000, 98, 2, 4, 19923), + PLL_36XX_RATE(67737602, 90, 2, 4, 20762), + PLL_36XX_RATE(49152000, 98, 3, 4, 19923), + PLL_36XX_RATE(45158401, 90, 3, 4, 20762), + PLL_36XX_RATE(32768001, 131, 3, 5, 4719), + { }, +}; + +static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(533000000, 533, 6, 2), + PLL_35XX_RATE(480000000, 160, 2, 2), + PLL_35XX_RATE(420000000, 140, 2, 2), + PLL_35XX_RATE(350000000, 175, 3, 2), + PLL_35XX_RATE(266000000, 266, 3, 3), + PLL_35XX_RATE(177000000, 118, 2, 3), + PLL_35XX_RATE(100000000, 200, 3, 4), + { }, +}; + /* register exynos5420 clocks */ static void __init exynos5420_clk_init(struct device_node *np) { @@ -776,6 +846,14 @@ static void __init exynos5420_clk_init(struct device_node *np) samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), ext_clk_match); + + if (_get_rate("fin_pll") == 24 * MHZ) { + exynos5420_plls[apll].rate_table = apll_24mhz_tbl; + exynos5420_plls[kpll].rate_table = kpll_24mhz_tbl; + exynos5420_plls[epll].rate_table = epll_24mhz_tbl; + exynos5420_plls[vpll].rate_table = vpll_24mhz_tbl; + } + samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls), reg_base); samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,