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Wed, 25 Jan 2017 11:56:00 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi , Inki Dae Subject: [PATCH 3/8] arm64: dts: exynos: Add DISP power domain to Exynos 5433 SoC Date: Wed, 25 Jan 2017 12:55:37 +0100 Message-id: <1485345342-3273-4-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1485345342-3273-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrEIsWRmVeSWpSXmKPExsWy7djPc7oBkzoiDJbP1rbYOGM9q8X1L89Z LSbdn8Bicf78BnaLz71HGC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6MG59uMResl6w4OGsKSwPjT+EuRk4OCQETiafLZjNC2GISF+6tZwOxhQSW MkpMnCACYX9mlPi6QxKm/sXJuyxdjFxA8WWMEtcWHYdyGpgk5n37zQJSxSZgKNH1tgtskoiA vcTtJ8vYQYqYBdqYJHbdamMFSQgLBEvcbV0NtppFQFXi0aOfYM28Au4St+ZcZIVYJydx8thk MJtTwEOi62k/E8ggCYHXbBJn5u4BauYAcmQlNh1ghqh3kVi+qJUNwhaWeHV8CzuELSPR2XGQ CcLuZ5RoatWGsGcwSpx7ywthW0scPg6xl1mAT2LStunMEON5JTrahCBMD4kXa6EB4Shx4fVK dojfZwNN7GpmmsAos4CRYRWjSGppcW56arGJXnFibnFpXrpecn7uJkZgzJ7+d/zLDsbFx6wO MQpwMCrx8L5IaY8QYk0sK67MPcQowcGsJMIrPbEjQog3JbGyKrUoP76oNCe1+BCjNAeLkjjv ngVXwoUE0hNLUrNTUwtSi2CyTBycUg2MXXWqYUHz+2ZtmavXwRTWLC8sy33pY41ll1ffCpPt Wpp/uu2a3sWue3H8ysUz95tWR+TnfXGa/q56vtGJK7cmup9i3Zm3y/f0kfvJUx6dO6jA0jkl JvzC+VN6j/+FTPgaK3CsZ83c74s/p0/L/poj8kW9/HWJ9asvDOdLnUylPz0JXZ7Reu+QpxJL cUaioRZzUXEiAOM6KbTVAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrKLMWRmVeSWpSXmKPExsVy+t/xK7r9kzoiDL6dkrLYOGM9q8X1L89Z LSbdn8Bicf78BnaLz71HGC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKDeb jNTElNQihdS85PyUzLx0W6XQEDddCyWFvMTcVFulCF3fkCAlhbLEnFIgz8gADTg4B7gHK+nb Jbhl3Ph0i7lgvWTFwVlTWBoYfwp3MXJySAiYSLw4eZcFwhaTuHBvPVsXIxeHkMASRokTBz+w QjhNTBINX7YzgVSxCRhKdL3tYgOxRQTsJW4/WcYOUsQs0MEk8e9OC1hCWCBYovVDI1gDi4Cq xKNHP8FW8Aq4S9yac5EVYp2cxMljk8FsTgEPia6n/WD1QkA1U2+uZZnAyLuAkWEVo0hqaXFu em6xoV5xYm5xaV66XnJ+7iZGYBBvO/Zz8w7GSxuDDzEKcDAq8fBOSGqPEGJNLCuuzD3EKMHB rCTC69DSESHEm5JYWZValB9fVJqTWnyI0RToqInMUqLJ+cAIyyuJNzQxNLc0NDK2sDA3MlIS 5y35cCVcSCA9sSQ1OzW1ILUIpo+Jg1OqgbH/YNUM667OH95llYxLZ0x5xbTlVPCiukMPM/0S AzYt0XHhKvji3jKzIvXbWdPbt/4stJiiuyXK5NfFQsmfQR8XCimY+2p4l580Y3hbWxR7puni Zv6wN/2p/Wd+XhLhVJz3X8py54PmafftLJOb7yaHd5m8zls5/YVLhNNZvkUJZfku3qecXyix FGckGmoxFxUnAgAODCLceAIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170125115600eucas1p1e9b1adbb62380568f94793d1de17cdc2 X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170125115600eucas1p1e9b1adbb62380568f94793d1de17cdc2 X-RootMTR: 20170125115600eucas1p1e9b1adbb62380568f94793d1de17cdc2 References: <1485345342-3273-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This patch adds support for DISP power domain to Exynos 5433 SoCs, which contains following devices: a clock controller, two display controllers (DECON and DECON TV), their SYSMMUs, MIC, DSI and HDMI video devices. OCSigned-off-by: Marek Szyprowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 74c767d756ac..a84b44cea2a8 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -368,6 +368,7 @@ <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, <&cmu_mif CLK_ACLK_DISP_333>; + power-domains = <&pd_disp>; }; cmu_aud: clock-controller@114c0000 { @@ -532,6 +533,12 @@ #power-domain-cells = <0>; }; + pd_disp: disp-power-domain@105c4080 { + compatible = "samsung,exynos5433-pd"; + reg = <0x105c4080 0x20>; + #power-domain-cells = <0>; + }; + tmu_atlas0: tmu@10060000 { compatible = "samsung,exynos5433-tmu"; reg = <0x10060000 0x200>; @@ -735,6 +742,7 @@ clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x", "pclk_smmu_decon0x", "sclk_decon_vclk", "sclk_decon_eclk"; + power-domains = <&pd_disp>; interrupt-names = "fifo", "vsync", "lcd_sys"; interrupts = , , @@ -772,6 +780,7 @@ "aclk_xiu_decon0x", "pclk_smmu_decon0x", "sclk_decon_vclk", "sclk_decon_eclk"; samsung,disp-sysreg = <&syscon_disp>; + power-domains = <&pd_disp>; interrupt-names = "fifo", "vsync", "lcd_sys"; interrupts = , , @@ -797,6 +806,7 @@ "phyclk_mipidphy0_rxclkesc0", "sclk_rgb_vclk_to_dsim0", "sclk_mipi"; + power-domains = <&pd_disp>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -820,6 +830,7 @@ clocks = <&cmu_disp CLK_PCLK_MIC0>, <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; + power-domains = <&pd_disp>; samsung,disp-syscon = <&syscon_disp>; status = "disabled"; @@ -961,6 +972,7 @@ clock-names = "pclk", "aclk"; clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>; + power-domains = <&pd_disp>; #iommu-cells = <0>; }; @@ -972,6 +984,7 @@ clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>, <&cmu_disp CLK_ACLK_SMMU_DECON1X>; #iommu-cells = <0>; + power-domains = <&pd_disp>; }; sysmmu_tv0x: sysmmu@13a20000 { @@ -982,6 +995,7 @@ clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>, <&cmu_disp CLK_ACLK_SMMU_TV0X>; #iommu-cells = <0>; + power-domains = <&pd_disp>; }; sysmmu_tv1x: sysmmu@13a30000 { @@ -992,6 +1006,7 @@ clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>, <&cmu_disp CLK_ACLK_SMMU_TV1X>; #iommu-cells = <0>; + power-domains = <&pd_disp>; }; sysmmu_gscl0: sysmmu@13c80000 {