@@ -2025,6 +2025,28 @@ static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = {
.n_regulators = ARRAY_SIZE(exynos5_regulator_names),
};
+static const struct phy_ops exynosautov920_usbdrd_phy_ops = {
+ .init = exynos850_usbdrd_phy_init,
+ .exit = exynos850_usbdrd_phy_exit,
+ .owner = THIS_MODULE,
+};
+
+static const struct exynos5_usbdrd_phy_config phy_cfg_exynosautov920[] = {
+ {
+ .id = EXYNOS5_DRDPHY_UTMI,
+ .phy_init = exynos850_usbdrd_utmi_init,
+ },
+};
+
+static const struct exynos5_usbdrd_phy_drvdata exynosautov920_usbdrd_phy = {
+ .phy_cfg = phy_cfg_exynosautov920,
+ .phy_ops = &exynosautov920_usbdrd_phy_ops,
+ .clk_names = exynos5_clk_names,
+ .n_clks = ARRAY_SIZE(exynos5_clk_names),
+ .core_clk_names = exynos5_core_clk_names,
+ .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
+};
+
static const struct exynos5_usbdrd_phy_config phy_cfg_gs101[] = {
{
.id = EXYNOS5_DRDPHY_UTMI,
@@ -2228,6 +2250,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
}, {
.compatible = "samsung,exynos850-usbdrd-phy",
.data = &exynos850_usbdrd_phy
+ }, {
+ .compatible = "samsung,exynosautov920-usbdrd-phy",
+ .data = &exynosautov920_usbdrd_phy
},
{ },
};
This SoC has a single USB 3.1 DRD combo phy that supports both UTMI+ (HS) and PIPE3 (SS) and three USB2.0 DRD HS phy controllers those only support the UTMI+ (HS) interface. Support only UTMI+ port for this SoC which is very similar to what the existing Exynos850 supports. The combo phy support is out of scope of this commit. Add required change in phy driver to support HS phy for this SoC. Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com> --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+)