@@ -88,6 +88,18 @@ &xtcxo {
};
/* usb */
+&usbdrd31_hsphy {
+ status = "okay";
+};
+
+&usbdrd31_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usbdrd31 {
+ status = "okay";
+};
+
&usbdrd20_phy0 {
status = "okay";
};
@@ -1048,6 +1048,17 @@ pinctrl_hsi1: pinctrl@16450000 {
interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
};
+ usbdrd31_hsphy: phy@16490000 {
+ compatible = "samsung,exynosautov920-usbdrd-hsphy";
+ reg = <0x16490000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
usbdrd20_phy0: phy@16500000 {
compatible = "samsung,exynosautov920-usbdrd-phy";
reg = <0x16500000 0x0200>;
@@ -1081,6 +1092,31 @@ usbdrd20_phy2: phy@16520000 {
status = "disabled";
};
+ usbdrd31: usb@16600000 {
+ compatible = "samsung,exynosautov920-dwusb3";
+ ranges = <0x0 0x16600000 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd31_dwc3: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ interrupts = <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd31_hsphy 0>;
+ phy-names = "usb2-phy";
+ snps,has-lpm-erratum;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
usbdrd20_0: usb@16700000 {
compatible = "samsung,exynosautov920-dwusb3";
ranges = <0x0 0x16700000 0x10000>;
Add the USB 3.1 DRD controller and USB31DRD HS combo phy nodes for ExynosAutov920 soc. The USB 3.1 DRD controller has the following features: * DWC3 compatible * compliant with both USB device 3.1 and USB device 2.0 standards * compliant with USB host 3.1 and USB host 2.0 standards * supports USB device 3.1 and USB device 2.0 interfaces * supports USB host 3.1 and USB host 2.0 interfaces * full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device 2.0 interface * super-speed (5 Gbps) mode with USB device 3.1 Gen1 interface * super-speed plus (10 Gbps) mode with USB device 3.1 Gen2 interface * single USB port which can be used for USB 3.1 or USB 2.0 * on-chip USB PHY transceiver * supports up to 16 bi-directional endpoints * compliant with xHCI 1.1 specification Only UTMI+ is supported in this commit, so only UTMI+ PHY interface is specified in "phys" property (index 0) and PIPE3 is omitted (index 1). Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com> --- .../boot/dts/exynos/exynosautov920-sadk.dts | 12 +++++++ .../arm64/boot/dts/exynos/exynosautov920.dtsi | 36 +++++++++++++++++++ 2 files changed, 48 insertions(+)