| Message ID | 20231012172129.65172-1-manivannan.sadhasivam@linaro.org |
|---|---|
| Headers | show |
| Series | UFS: Add OPP support | expand |
On Thu, Oct 12, 2023 at 10:51:24PM +0530, Manivannan Sadhasivam wrote: > Hi, > > This series adds OPP (Operating Points) support to UFSHCD driver. > > Motivation behind adding OPP support is to scale both clocks as well as > regulators/performance state dynamically. Currently, UFSHCD just scales > clock frequency during runtime with the help of "freq-table-hz" property > defined in devicetree. With the addition of OPP tables in devicetree (as > done for Qcom SDM845 and SM8250 SoCs in this series) UFSHCD can now scale > both clocks and performance state of power domain which helps in power > saving. > > For the addition of OPP support to UFSHCD, there are changes required to > the OPP framework and devfreq drivers. The OPP framework changes are already > merged and the devfreq change is added in this series. > > Credits > ======= > > This series is a continuation of previous work by Krzysztof Kozlowski [1]. > > Testing > ======= > > This series is tested on 96Boards RB3 (SDM845 SoC) and RB5 (SM8250 SoC) > development boards. > > Merging Strategy > ================ > > Since the devfreq patch got an Ack from the maintainer, either it can be merged > to scsi tree with rest of the patches or merged separately through devfreq tree. > Martin, can you please merge the ufs patches (drivers,bindings) for v6.7? Note that the devfreq patch already got merged and the above text is outdated (my bad). - Mani > Thanks, > Mani > > [1] https://lore.kernel.org/all/20220513061347.46480-1-krzysztof.kozlowski@linaro.org/ > > Changes in v7: > > * Added missing EXPORT_SYMBOL_GPL() for ufshcd_opp_config_clks() API as reported > by Alessandro Carminati > > Changes in v6: > > * Collected tags from Dmitry > * Fixed bindings issues reported by Krzysztof > > Changes in v5: > > * Dropped the devfreq patch since it got applied > * Fixed the bindings issue reported by DT bot > * Rebased on top of mkp/scsi/for-next > > Changes in v4: > > * Rebased on top of v6.6-rc3 > > Changes in v3: > > * Rebased on top of linux-next/master tag: next-20230731 > * Dropped the already applied patches (dts, opp binding and framework) > * Moved the interconnect patches to a separate series: > https://lore.kernel.org/linux-scsi/20230731145020.41262-1-manivannan.sadhasivam@linaro.org/ > * Moved ufshcd_opp_config_clks() API to ufshcd.c to fix the build failure > reported by Kbuild bot: https://lore.kernel.org/all/202307210542.KoLHRbU6-lkp@intel.com/ > * Collected Acks > * v2: https://lore.kernel.org/all/20230720054100.9940-1-manivannan.sadhasivam@linaro.org/ > > Changes in v2: > > * Added more description to the bindings patch 2/15 > * Fixed dev_pm_opp_put() usage in patch 10/15 > * Added a new patch for adding enums for UFS lanes 14/15 > * Changed the icc variables to mem_bw and cfg_bw and used > the enums for gears and lanes in bw_table > * Collected review tags > * Added SCSI list and folks > * Removed duplicate patches > > Krzysztof Kozlowski (2): > dt-bindings: ufs: common: add OPP table > arm64: dts: qcom: sdm845: Add OPP table support to UFSHC > > Manivannan Sadhasivam (3): > scsi: ufs: core: Add OPP support for scaling clocks and regulators > scsi: ufs: host: Add support for parsing OPP > arm64: dts: qcom: sm8250: Add OPP table support to UFSHC > > .../devicetree/bindings/ufs/ufs-common.yaml | 35 +++- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 42 +++- > arch/arm64/boot/dts/qcom/sm8250.dtsi | 39 +++- > drivers/ufs/core/ufshcd.c | 180 ++++++++++++++---- > drivers/ufs/host/ufshcd-pltfrm.c | 78 ++++++++ > include/ufs/ufshcd.h | 7 + > 6 files changed, 326 insertions(+), 55 deletions(-) > > -- > 2.25.1 >
Manivannan, > Martin, can you please merge the ufs patches (drivers,bindings) for > v6.7? Note that the devfreq patch already got merged and the above > text is outdated (my bad). Applied to 6.7/scsi-staging, thanks!
On Sat, Dec 02, 2023 at 08:54:46PM -0800, Bjorn Andersson wrote: > > On Thu, 12 Oct 2023 22:51:24 +0530, Manivannan Sadhasivam wrote: > > This series adds OPP (Operating Points) support to UFSHCD driver. > > > > Motivation behind adding OPP support is to scale both clocks as well as > > regulators/performance state dynamically. Currently, UFSHCD just scales > > clock frequency during runtime with the help of "freq-table-hz" property > > defined in devicetree. With the addition of OPP tables in devicetree (as > > done for Qcom SDM845 and SM8250 SoCs in this series) UFSHCD can now scale > > both clocks and performance state of power domain which helps in power > > saving. > > > > [...] > > Applied, thanks! > > [4/5] arm64: dts: qcom: sdm845: Add OPP table support to UFSHC > commit: ec987b5efd59fdea4178d824d8ec4bbdf3019bdf > [5/5] arm64: dts: qcom: sm8250: Add OPP table support to UFSHC > commit: 725be1d6318e4ea7e3947fd4242a14cf589cfebf > Bjorn, could you please drop these two patches? I found the OPP regression in the ufs-qcom driver due to some patches that got merged last cycle. Nitin is working on a fix for that. So I'd like to defer merging of these dts patches to v6.9. I can resend them after v6.8-rc1. - Mani > Best regards, > -- > Bjorn Andersson <andersson@kernel.org>
On 12.10.2023 19:21, Manivannan Sadhasivam wrote: > UFS host controller, when scaling gears, should choose appropriate > performance state of RPMh power domain controller along with clock > frequency. So let's add the OPP table support to specify both clock > frequency and RPMh performance states replacing the old "freq-table-hz" > property. > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- This patch landed in today's linux-next as commit 725be1d6318e ("arm64: dts: qcom: sm8250: Add OPP table support to UFSHC"). Unfortunately it breaks booting of my RB5 board with the following messages: ufshcd-qcom 1d84000.ufshc: Adding to iommu group 5 ufshcd-qcom 1d84000.ufshc: freq-table-hz property not specified ufshcd-qcom 1d84000.ufshc: ufshcd_populate_vreg: Unable to find vdd-hba-supply regulator, assuming enabled ufshcd-qcom 1d84000.ufshc: freq-table-hz property not specified ufshcd-qcom 1d84000.ufshc: ufshcd_populate_vreg: Unable to find vdd-hba-supply regulator, assuming enabled scsi host0: ufshcd ufshcd-qcom 1d84000.ufshc: UNIPRO clk freq 0 MHz not supported ufshcd-qcom 1d84000.ufshc: cfg core clk ctrl failed clk: Disabling unused clocks ALSA device list: No soundcards found. Waiting 2 sec before mounting root device... ufshcd-qcom 1d84000.ufshc: uic cmd 0x16 with arg3 0x0 completion timeout ufshcd-qcom 1d84000.ufshc: Controller enable failed ufshcd-qcom 1d84000.ufshc: Controller enable failed ufshcd-qcom 1d84000.ufshc: Controller enable failed ufshcd-qcom 1d84000.ufshc: Controller enable failed ufshcd-qcom 1d84000.ufshc: link startup failed -110 ufshcd-qcom 1d84000.ufshc: UFS Host state=0 ufshcd-qcom 1d84000.ufshc: outstanding reqs=0x0 tasks=0x0 ufshcd-qcom 1d84000.ufshc: saved_err=0x0, saved_uic_err=0x0 ufshcd-qcom 1d84000.ufshc: Device power mode=1, UIC link state=0 ufshcd-qcom 1d84000.ufshc: PM in progress=0, sys. suspended=0 ufshcd-qcom 1d84000.ufshc: Auto BKOPS=0, Host self-block=0 ufshcd-qcom 1d84000.ufshc: Clk gate=1 ufshcd-qcom 1d84000.ufshc: last_hibern8_exit_tstamp at 0 us, hibern8_exit_cnt=0 ufshcd-qcom 1d84000.ufshc: last intr at 2889168 us, last intr status=0x400 ufshcd-qcom 1d84000.ufshc: error handling flags=0x0, req. abort count=0 ufshcd-qcom 1d84000.ufshc: hba->ufs_version=0x300, Host capabilities=0x1587031f, caps=0x12cf ufshcd-qcom 1d84000.ufshc: quirks=0x80000, dev. quirks=0x0 host_regs: 00000000: 1587031f 00000000 00000300 00000000 host_regs: 00000010: 01000000 00010217 00000000 00000000 host_regs: 00000020: 00000000 00000000 00000000 00000000 host_regs: 00000030: 00000008 00000000 00000000 00000000 host_regs: 00000040: 00000000 00000000 00000000 00000000 host_regs: 00000050: 00000000 00000000 00000000 00000000 host_regs: 00000060: 00000000 00000000 00000000 00000000 host_regs: 00000070: 00000000 00000000 00000000 00000000 host_regs: 00000080: 00000000 00000000 00000000 00000000 host_regs: 00000090: 00000000 00000001 00000000 00000000 ufshcd-qcom 1d84000.ufshc: No record of pa_err ufshcd-qcom 1d84000.ufshc: No record of dl_err ufshcd-qcom 1d84000.ufshc: No record of nl_err ufshcd-qcom 1d84000.ufshc: No record of tl_err ufshcd-qcom 1d84000.ufshc: No record of dme_err ufshcd-qcom 1d84000.ufshc: No record of auto_hibern8_err ufshcd-qcom 1d84000.ufshc: No record of fatal_err ufshcd-qcom 1d84000.ufshc: link_startup_fail[0] = 0xffffff92 at 3663462 us ufshcd-qcom 1d84000.ufshc: link_startup_fail: total cnt=1 ufshcd-qcom 1d84000.ufshc: No record of resume_fail ufshcd-qcom 1d84000.ufshc: No record of suspend_fail ufshcd-qcom 1d84000.ufshc: No record of wlun resume_fail ufshcd-qcom 1d84000.ufshc: No record of wlun suspend_fail ufshcd-qcom 1d84000.ufshc: No record of dev_reset ufshcd-qcom 1d84000.ufshc: No record of host_reset ufshcd-qcom 1d84000.ufshc: No record of task_abort HCI Vendor Specific Registers 00000000: 0000012c 00000000 00000000 00000000 HCI Vendor Specific Registers 00000010: 00000042 00000000 00000001 1c00052c HCI Vendor Specific Registers 00000020: 3f011300 40020000 00000000 00000000 HCI Vendor Specific Registers 00000030: 00000000 00000000 00000000 00000000 UFS_UFS_DBG_RD_REG_OCSC 00000000: 00000000 00000000 00000000 00000000 UFS_UFS_DBG_RD_REG_OCSC 00000010: 00000000 00000000 00000000 00000000 UFS_UFS_DBG_RD_REG_OCSC 00000020: 00000000 00000000 00000000 00000000 UFS_UFS_DBG_RD_REG_OCSC 00000030: 00000000 00000000 00000000 00000000 UFS_UFS_DBG_RD_REG_OCSC 00000040: 00000000 00000000 00000000 00000000 UFS_UFS_DBG_RD_REG_OCSC 00000050: 00000000 00000000 00000000 00000000 UFS_UFS_DBG_RD_REG_OCSC 00000060: 00000000 00000000 00000000 00000000 UFS_UFS_DBG_RD_REG_OCSC 00000070: 00000000 00000000 00000000 00000000 UFS_UFS_DBG_RD_REG_OCSC 00000080: 00000000 00000000 00000000 00000000 UFS_UFS_DBG_RD_REG_OCSC 00000090: 00000000 00000000 00000000 00000000 UFS_UFS_DBG_RD_REG_OCSC 000000a0: 00000000 00000000 00000000 00000000 UFS_UFS_DBG_RD_EDTL_RAM 00000000: 00000000 7147f7fd 47857989 b7556f16 UFS_UFS_DBG_RD_EDTL_RAM 00000010: ad69b114 7cd5fd55 41d57796 0e55e717 UFS_UFS_DBG_RD_EDTL_RAM 00000020: 04558745 efc573b5 4f35f49b b2697d16 UFS_UFS_DBG_RD_EDTL_RAM 00000030: 5c7563d5 7755f4d6 cf65dd90 6591d535 UFS_UFS_DBG_RD_EDTL_RAM 00000040: 4151f597 ffaf75a9 57442485 f7654511 UFS_UFS_DBG_RD_EDTL_RAM 00000050: fc57e046 ff57f5b5 c7c53417 adb56f55 UFS_UFS_DBG_RD_EDTL_RAM 00000060: 9b753f4c 5155a115 245525f1 77755d51 UFS_UFS_DBG_RD_EDTL_RAM 00000070: 5791ffdf 77555756 7cd5b941 431ce192 UFS_UFS_DBG_RD_DESC_RAM 00000000: 7dfffedf 001fbffb ff7fffff 003ffffd UFS_UFS_DBG_RD_DESC_RAM 00000010: 7f3dfff5 003fffff 7ffdfff3 0017fff7 UFS_UFS_DBG_RD_DESC_RAM 00000020: 3fdd595f 003ff5b7 ffffdfdf 003f77f7 UFS_UFS_DBG_RD_DESC_RAM 00000030: fffff7d7 003f75f7 7fffffff 0037ffff UFS_UFS_DBG_RD_DESC_RAM 00000040: fdff7f7f 003f57df fdfeffbf 003ffff7 UFS_UFS_DBG_RD_DESC_RAM 00000050: 7d7d7fff 00379d7f 7ffd7fff 001f3fff UFS_UFS_DBG_RD_DESC_RAM 00000060: 7f7fdeff 003fffd5 f7f7fffd 003fffff UFS_UFS_DBG_RD_DESC_RAM 00000070: 777ffd7d 003ffd75 ff7ffffd 003f7ffd UFS_UFS_DBG_RD_DESC_RAM 00000080: ff15fddf 003edfd7 df5ffff7 003fffdf UFS_UFS_DBG_RD_DESC_RAM 00000090: ffe57f5f 003fbff7 ddd7ff75 003f7fff UFS_UFS_DBG_RD_DESC_RAM 000000a0: fd4ffffd 003dddff eefffff7 003fbfff UFS_UFS_DBG_RD_DESC_RAM 000000b0: 67fffffd 001ff7fd bdd75f7f 0031bfff UFS_UFS_DBG_RD_DESC_RAM 000000c0: ffdddf75 003fff5d 7f5fffdd 002f7fdf UFS_UFS_DBG_RD_DESC_RAM 000000d0: ff7d5ffd 0037fdff df675fd5 001ffbdf UFS_UFS_DBG_RD_DESC_RAM 000000e0: b5ff7dff 00337ffc ff7ff7fb 003ffff7 UFS_UFS_DBG_RD_DESC_RAM 000000f0: 5ffdffdd 001ddfff 75ffddff 003fffff UFS_UFS_DBG_RD_DESC_RAM 00000100: ff5f5fdf 003d37bf ff77dfff 0017edb7 UFS_UFS_DBG_RD_DESC_RAM 00000110: ff7ff7ff 003ffd7f ff5f7fdd 003f3fd7 UFS_UFS_DBG_RD_DESC_RAM 00000120: 7fffffdf 003ff5d9 55ffffdf 003f79d5 UFS_UFS_DBG_RD_DESC_RAM 00000130: d5ffe7f5 002767fe ffdd75df 003d7fdf UFS_UFS_DBG_RD_DESC_RAM 00000140: 7fff77ff 003dff5f 7d7ff7ff 002f7fff UFS_UFS_DBG_RD_DESC_RAM 00000150: fdff7ddf 003fe7dd 5df77ddd 0037f7ff UFS_UFS_DBG_RD_DESC_RAM 00000160: f7f16977 003f9fdf 5775ff77 00357ff5 UFS_UFS_DBG_RD_DESC_RAM 00000170: 7ffdfffb 003dff5f 7f7f77f7 003fffff UFS_UFS_DBG_RD_DESC_RAM 00000180: 57dff7df 003dffff fffdd7ff 001efffd UFS_UFS_DBG_RD_DESC_RAM 00000190: 7dffffed 003f7fce 77d9f7ff 001fdddd UFS_UFS_DBG_RD_DESC_RAM 000001a0: ddffdffd 001fd57d 7f7ff777 003f78dd UFS_UFS_DBG_RD_DESC_RAM 000001b0: d5eff77f 0037dfdf ed7d77ff 003ffffd UFS_UFS_DBG_RD_DESC_RAM 000001c0: cf7fdfff 001f5f7e ffffffff 003f57df UFS_UFS_DBG_RD_DESC_RAM 000001d0: fdfffffd 003f7dff 556ffddf 003fdd7f UFS_UFS_DBG_RD_DESC_RAM 000001e0: fdff71df 003e7fff ff3f7fd7 0037f77b UFS_UFS_DBG_RD_DESC_RAM 000001f0: 7f7f7677 00355fdf 7feffdff 0037ffff UFS_UFS_DBG_RD_PRDT_RAM 00000000: d1700001 0000192c 3d9edf71 00075d51 UFS_UFS_DBG_RD_PRDT_RAM 00000010: 4561073f 0000415d ddde6dd9 000ff55f UFS_UFS_DBG_RD_PRDT_RAM 00000020: adb7185f 000df971 579caffd 000de54d UFS_UFS_DBG_RD_PRDT_RAM 00000030: 45e55747 00057559 7f5e5dbd 000377df UFS_UFS_DBG_RD_PRDT_RAM 00000040: dd175467 0007dc9c 4e775d77 0007555f UFS_UFS_DBG_RD_PRDT_RAM 00000050: 1f15dd77 000d195d f1c9e535 0007b75f UFS_UFS_DBG_RD_PRDT_RAM 00000060: 15bd75f3 0007675f dfd59d77 00057b5c UFS_UFS_DBG_RD_PRDT_RAM 00000070: d4f09dee 00017d39 52857d56 000c6ddd UFS_UFS_DBG_RD_PRDT_RAM 00000080: c333fcd6 000545df 1d57f51d 000577e9 UFS_UFS_DBG_RD_PRDT_RAM 00000090: 9f83d45d 00055d18 d4e7d7ee 000713df UFS_UFS_DBG_RD_PRDT_RAM 000000a0: fdfe39d7 000754df d54f5d77 000746f1 UFS_UFS_DBG_RD_PRDT_RAM 000000b0: 5a40c5f5 000c45d4 17471fe3 000e9d1d UFS_UFS_DBG_RD_PRDT_RAM 000000c0: 1747dd5f 00074577 d540d75d 00044d67 UFS_UFS_DBG_RD_PRDT_RAM 000000d0: de3545d3 000c4757 5f845115 00063795 UFS_UFS_DBG_RD_PRDT_RAM 000000e0: d15d776c 000c7fd5 1f5f5d75 00067d75 UFS_UFS_DBG_RD_PRDT_RAM 000000f0: d71d4c7d 0007bd13 7557d77d 000355df UFS_DBG_RD_REG_UAWM 00000000: 00000000 0fe00000 00000004 f4000102 UFS_DBG_RD_REG_UARM 00000000: 00000000 00000000 00000001 00000001 UFS_DBG_RD_REG_TXUC 00000000: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TXUC 00000010: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TXUC 00000020: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TXUC 00000030: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TXUC 00000040: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TXUC 00000050: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TXUC 00000060: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TXUC 00000070: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TXUC 00000080: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TXUC 00000090: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TXUC 000000a0: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TXUC 000000b0: 00000001 00000000 00000000 00000004 UFS_DBG_RD_REG_RXUC 00000000: 00000000 00000000 00000000 00000004 UFS_DBG_RD_REG_RXUC 00000010: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_RXUC 00000020: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_RXUC 00000030: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_RXUC 00000040: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_RXUC 00000050: 00000000 00000000 00000000 00000001 UFS_DBG_RD_REG_RXUC 00000060: 00000000 00000000 00000004 UFS_DBG_RD_REG_DFC 00000000: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_DFC 00000010: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_DFC 00000020: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_DFC 00000030: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_DFC 00000040: ffffffff 00000000 00000000 UFS_DBG_RD_REG_TRLUT 00000000: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TRLUT 00000010: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TRLUT 00000020: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TRLUT 00000030: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TRLUT 00000040: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TRLUT 00000050: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TRLUT 00000060: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TRLUT 00000070: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TRLUT 00000080: 00000000 00000000 UFS_DBG_RD_REG_TMRLUT 00000000: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TMRLUT 00000010: 00000000 00000000 00000000 00000000 UFS_DBG_RD_REG_TMRLUT 00000020: 00000000 ------------[ cut here ]------------ gcc_ufs_phy_axi_clk status stuck at 'off' WARNING: CPU: 3 PID: 103 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x144/0x15c Modules linked in: CPU: 3 PID: 103 Comm: kworker/u17:0 Not tainted 6.7.0-rc4-next-20231205 #14278 Hardware name: Qualcomm Technologies, Inc. Robotics RB5 (DT) Workqueue: ufs_clk_gating_0 ufshcd_ungate_work pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : clk_branch_wait+0x144/0x15c lr : clk_branch_wait+0x144/0x15c sp : ffff80008160bc20 x29: ffff80008160bc20 x28: ffffa967de7ea200 x27: 0000000000000000 x26: ffff03ffc7bb18e8 x25: 0000000112be0f33 x24: 0000000000000001 x23: ffffa967dd981888 x22: 0000000000000001 x21: ffffa967dc27166c x20: 0000000000000000 x19: ffffa967deae9920 x18: 0000000000000038 x17: 0000000000000000 x16: 0000000000003ff1 x15: fffffffffffe9c68 x14: ffffa967de815360 x13: 0000000000000669 x12: 0000000000000223 x11: fffffffffffe9c68 x10: fffffffffffe9c30 x9 : 00000000fffff223 x8 : ffffa967de815360 x7 : ffffa967de86d360 x6 : 00000000000019a4 x5 : 000000000000bff4 x4 : 00000000fffff223 x3 : 0000000000000000 x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff03ffc7266500 Call trace: clk_branch_wait+0x144/0x15c clk_branch2_enable+0x30/0x40 clk_core_enable+0xe8/0x284 clk_enable+0x2c/0x4c ufshcd_setup_clocks+0x268/0x3d4 ufshcd_ungate_work+0xc0/0x134 process_one_work+0x1ec/0x53c worker_thread+0x298/0x408 kthread+0x124/0x128 ret_from_fork+0x10/0x20 irq event stamp: 76 hardirqs last enabled at (75): [<ffffa967dcc9ced0>] _raw_spin_unlock_irq+0x30/0x6c hardirqs last disabled at (76): [<ffffa967dc224250>] clk_enable_lock+0x7c/0xf0 softirqs last enabled at (0): [<ffffa967dbb186c8>] copy_process+0x650/0x21d8 softirqs last disabled at (0): [<0000000000000000>] 0x0 ---[ end trace 0000000000000000 ]--- ufshcd-qcom 1d84000.ufshc: ufshcd_setup_clocks: core_clk prepare enable failed, -16 Let me know if you need more logs or information. > arch/arm64/boot/dts/qcom/sm8250.dtsi | 39 +++++++++++++++++++++------- > 1 file changed, 30 insertions(+), 9 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index a4e58ad731c3..33abd84aae53 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -2198,21 +2198,42 @@ ufs_mem_hc: ufshc@1d84000 { > <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, > <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; > - freq-table-hz = > - <37500000 300000000>, > - <0 0>, > - <0 0>, > - <37500000 300000000>, > - <0 0>, > - <0 0>, > - <0 0>, > - <0 0>; > + > + operating-points-v2 = <&ufs_opp_table>; > > interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>, > <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>; > interconnect-names = "ufs-ddr", "cpu-ufs"; > > status = "disabled"; > + > + ufs_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-37500000 { > + opp-hz = /bits/ 64 <37500000>, > + /bits/ 64 <0>, > + /bits/ 64 <0>, > + /bits/ 64 <37500000>, > + /bits/ 64 <0>, > + /bits/ 64 <0>, > + /bits/ 64 <0>, > + /bits/ 64 <0>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>, > + /bits/ 64 <0>, > + /bits/ 64 <0>, > + /bits/ 64 <300000000>, > + /bits/ 64 <0>, > + /bits/ 64 <0>, > + /bits/ 64 <0>, > + /bits/ 64 <0>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > }; > > ufs_mem_phy: phy@1d87000 { Best regards