diff mbox series

[v5,7/7] arm64: dts: rockchip: Add UFS support for RK3576 SoC

Message ID 1731048987-229149-8-git-send-email-shawn.lin@rock-chips.com
State New
Headers show
Series Initial support for RK3576 UFS controller | expand

Commit Message

Shawn Lin Nov. 8, 2024, 6:56 a.m. UTC
Add ufshc node to rk3576.dtsi, so the board using UFS could
enable it.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm64/boot/dts/rockchip/rk3576.dtsi | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

Comments

Manivannan Sadhasivam Nov. 23, 2024, 5:04 a.m. UTC | #1
On Fri, Nov 08, 2024 at 02:56:26PM +0800, Shawn Lin wrote:
> Add ufshc node to rk3576.dtsi, so the board using UFS could
> enable it.
> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
> 
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  arch/arm64/boot/dts/rockchip/rk3576.dtsi | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> index 436232f..32beda2 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> @@ -1110,6 +1110,31 @@
>  			};
>  		};
>  
> +		ufshc: ufshc@2a2d0000 {
> +			compatible = "rockchip,rk3576-ufshc";
> +			reg = <0x0 0x2a2d0000 0 0x10000>, /* 0: HCI standard */
> +			      <0x0 0x2b040000 0 0x10000>, /* 1: Mphy */
> +			      <0x0 0x2601f000 0 0x1000>,  /* 2: HCI Vendor specified */
> +			      <0x0 0x2603c000 0 0x1000>,  /* 3: Mphy Vendor specified */
> +			      <0x0 0x2a2e0000 0 0x10000>; /* 4: HCI apb */

No need to add comments for each region. Bindings describe them.

- Mani
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 436232f..32beda2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1110,6 +1110,31 @@ 
 			};
 		};
 
+		ufshc: ufshc@2a2d0000 {
+			compatible = "rockchip,rk3576-ufshc";
+			reg = <0x0 0x2a2d0000 0 0x10000>, /* 0: HCI standard */
+			      <0x0 0x2b040000 0 0x10000>, /* 1: Mphy */
+			      <0x0 0x2601f000 0 0x1000>,  /* 2: HCI Vendor specified */
+			      <0x0 0x2603c000 0 0x1000>,  /* 3: Mphy Vendor specified */
+			      <0x0 0x2a2e0000 0 0x10000>; /* 4: HCI apb */
+			reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb";
+			clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>,
+				 <&cru CLK_REF_UFS_CLKOUT>;
+			clock-names = "core", "pclk", "pclk_mphy", "ref_out";
+			assigned-clocks = <&cru CLK_REF_OSC_MPHY>;
+			assigned-clock-parents = <&cru CLK_REF_MPHY_26M>;
+			interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&power RK3576_PD_USB>;
+			pinctrl-0 = <&ufs_refclk>;
+			pinctrl-names = "default";
+			resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>,
+				 <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>;
+			reset-names = "biu", "sys", "ufs", "grf";
+			reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>;
+			status = "disabled";
+		};
+
 		sdmmc: mmc@2a310000 {
 			compatible = "rockchip,rk3576-dw-mshc";
 			reg = <0x0 0x2a310000 0x0 0x4000>;
-- 
2.7.4