| Message ID | 20231006103959.197485-1-claudiu.beznea.uj@bp.renesas.com |
|---|---|
| Headers | show |
| Series | Add new Renesas RZ/G3S SoC and RZ/G3S SMARC EVK | expand |
On Fri, Oct 6, 2023 at 12:40 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Add a divider clock driver for RZ/G3S. This will be used in RZ/G3S > by SDHI, SPI, OCTA, I, I2, I3, P0, P1, P2, P3 core clocks. > The divider has some limitation for SDHI, OCTA and SPI clocks: > - SDHI div cannot be 1 if parent rate is 800MHz > - OCTA, SPI div cannot be 1 if parent rate is 400MHz > For these clocks a notifier could be registered from platform specific > clock driver and proper actions are taken before clock rate is changed, > if needed. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > > Changes in v3: > - adjusted commit message to specifies that divider has limitations also > for SPI clock > - s/SD div/SDHI div in commit message > - return proper code from notifier > - used CPG_WEN_BIT where possible notifier and set explicitily 1 in div > notifier > - removed rzg3s_div_clk_is_rate_valid() and all its occurencies: it was > not needed in rzg3s_div_clk_set_rate() > - .round_rate was replaced by .determine_rate for the introduced divider > - initialized max variable in rzg3s_cpg_div_clk_register() > - introduced struct div_hw_data::max_rate to specify from the SoC-specific > drivers the maximum available rate for divider that will be requested > when a rate higher than this one is requested > - removed bitmask variable from notifier and rzg3s_div_clk_set_rate() > - added max_rate to DEF_G3S_DIV() macro > - tested on RZ/G2L and RZ/G3S Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v6.7. Gr{oetje,eeting}s, Geert
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Hi, This patch series adds initial support for The Renesas RZ/G3S (R9A08G045{S33}) SoC. The RZ/G3S device is a general-purpose microprocessor with a single-core Arm® Cortex®-A55 (1.1GHz) and a dual-core Arm® Cortex®-M33 (250MHz), perfect for an IOT gateway controller. This includes: - SoC identification; - clocks (core clocks, pin controller clock, serial interface, SD ch0 clock) and corresponding resets; - minimal device tree for SoM and carrier boards. With this series Linux can boot from eMMC or SD card. The eMMC and uSD interface are multiplexed on the SoM; selection is made using a hardware switch. Patches are gouped as follows: - 01 documents scif support; - 02-04 clock changes needed by RZ/G3S Changes in v3: - remove from series patches that were already integrated - addressed review comments - please see individual patches for detailed changes Changes in v2: - addressed review comments - collected tags - removed from series patches that were already integrated - added patches: - [PATCH v2 19/28] dt-bindings: pinctrl: renesas: set additionalProperties: false - [PATCH v2 23/28] dt-bindings: arm: renesas: document RZ/G3S SMARC SoM - [PATCH v2 26/28] dt-bindings: arm: renesas: document SMARC Carrier-II EVK - please see individual patches for detailed changes Claudiu Beznea (4): dt-bindings: serial: renesas,scif: document r9a08g045 support clk: renesas: rzg2l: refactor sd mux driver clk: renesas: rzg2l: add a divider clock for RZ/G3S clk: renesas: add minimal boot support for RZ/G3S SoC .../bindings/serial/renesas,scif.yaml | 1 + drivers/clk/renesas/Kconfig | 7 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a07g043-cpg.c | 12 +- drivers/clk/renesas/r9a07g044-cpg.c | 12 +- drivers/clk/renesas/r9a08g045-cpg.c | 214 +++++++++++ drivers/clk/renesas/rzg2l-cpg.c | 342 +++++++++++++++--- drivers/clk/renesas/rzg2l-cpg.h | 28 +- 8 files changed, 565 insertions(+), 52 deletions(-) create mode 100644 drivers/clk/renesas/r9a08g045-cpg.c