From patchwork Wed Jul 31 19:56:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 170214 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp4434685ile; Wed, 31 Jul 2019 13:00:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqzDUsxHVawFz9SVi2vdLg/lomMhRLqcggyizaHVKrW4OGe70DnnRQx6ns65GY05+jdVGwPD X-Received: by 2002:aa7:9359:: with SMTP id 25mr47771794pfn.261.1564603242171; Wed, 31 Jul 2019 13:00:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564603242; cv=none; d=google.com; s=arc-20160816; b=GGOLWz7WgsU3KfcelkXIVLWC8pRgouiQ4Izlqg/xf6Z72bBTjQXNDK/H1+KnwpayVA j3T3eJ8td1lkZS8UcMlvklCk0vwwsHD/Nww4KrdYphWIZOH+s80VFk2UAammABQy6Z6W kY1WDZ0V9PYNpTW29Tl3xhBb7MaYDcbt3Ms5otWXSkA+iZdBLPlFBG3dtYYPNLl++9yT 7R5s98mbeNMkpJF/f4T+U0+x91ofny+mul0yoIK2FKyWBz76tsQ9HZbhZ3aB7bQe8s4S +ZHLb3jye661r1n4l347K103qTuHulUoHIWz5zN6I6X98ktYAWq0WIHH+8uwptQSirV6 r5bA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=294ZhmyY2l3qan8/Da1jCq7IwVqa1vI9tCxdzMvwmdk=; b=x6wyzYuDvDiztzpN4IqEEgi0yY6Ew+GcLa5WQ+C7yawvmNDe53jMcipaEOsvrHPsmi 3piCDOL114okqiCWj8R7udEpsK/vghDVzPfVYtsMEYOQnrbuO4UDfK8IKe0pB+fdTx+f npqaAVt6iK1csMzVPJa41n1ivDUhP2lptnhVWrE2gEN5VZo5R9YF8tFpYWF184vX4ne/ q5IXBzxLYobmIzFD5vQx5X1GK44XmBOLoy1UMAXmvIN4wSN/HkeLshNlKZqKVooMXVBP n5XA+85Ghm6p//Se9hQjbcfY3yEPGuofY7QIHT7DXOWXZOFdycBvDwtjjYcZj/1NSimv xS+Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v66si33711218pgb.584.2019.07.31.13.00.41; Wed, 31 Jul 2019 13:00:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728050AbfGaUAl (ORCPT + 1 other); Wed, 31 Jul 2019 16:00:41 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:39563 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725793AbfGaUAl (ORCPT ); Wed, 31 Jul 2019 16:00:41 -0400 Received: from threadripper.lan ([149.172.19.189]) by mrelayeu.kundenserver.de (mreue012 [212.227.15.129]) with ESMTPA (Nemesis) id 1MCGag-1i2EAl44sU-009SDz; Wed, 31 Jul 2019 22:00:02 +0200 From: Arnd Bergmann To: soc@kernel.org, linux-arm-kernel@lists.infradead.org, Vladimir Zapolskiy , Sylvain Lemieux , Russell King , Gregory Clement , Linus Walleij , Bartosz Golaszewski Cc: Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , "David S. Miller" , Greg Kroah-Hartman , Alan Stern , Guenter Roeck , linux-gpio@vger.kernel.org, netdev@vger.kernel.org, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, linux-watchdog@vger.kernel.org, Arnd Bergmann , Lee Jones , linux-kernel@vger.kernel.org Subject: [PATCH 05/14] gpio: lpc32xx: allow building on non-lpc32xx targets Date: Wed, 31 Jul 2019 21:56:47 +0200 Message-Id: <20190731195713.3150463-6-arnd@arndb.de> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20190731195713.3150463-1-arnd@arndb.de> References: <20190731195713.3150463-1-arnd@arndb.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:nPvPw9YMOaGoeG2QbL6aN8onQhuRLs7PBsNyvS/8jeZPiB2gXYm WBvj7CT/LrcyNxXCQEKzNhWdVnnmj3/03xr+BhLaTsTY+gJMV1XVz9qEE2q+1RAjiL848GO 3ROgAwuwkP7DloHoG9cMXG3IMfqi20QeI7miijXlSompfK6pMA5NdVHjCuVTSMVNKQMHBQv ET5ttUT9J8Urs8rYK1wFQ== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1; V03:K0:gPysoRTXsu8=:ez7tYz6ZrTKnZ1oPtqCtmg oO0Hqyg8T38hQ03POAmT8MiW64FttY5KCjqVWGK/r1ekR8Rv2ynx4MzliMVdJrRHNI4KWyMjH 58M9y1TxWf6YLBq8BEahuS1+AkO6hBPCyNXc8UUYb1+rqmqr9YSDzkLPUESlyK7lBpcurBh9J hHqMfUfNzY3hFNZ5ch0KJxZP9fCAO3t/qtfY3fSt4OtHgvJY//yWKPe7O3yOXVaY2Rs7EQ26u Fjk26HKsrY9t20yCK9YW5SsiD807oDapqJmc8NzKN+q0oth4f2DriZ3zugda8R+T/Vm5ysFnW vAJiq6zL8PP6UtQWYCx7Vnsj0gJlh7nfUEi4d8Rq+5r6Diub/Y7LGV3W9woilHpbn1hlKMW7l M8UF/nbKRI5SdgwesfA1zlEfFHs5HoiCymGjNLxG0Qp2rFAy++lwaCGliUTNKa2QO3DQbUDkQ M5xZDxk/BIxWh1fADMHgsaWeMWW3nYEezVOtSfOS2h+skjoAkAO7HKrTop4tseWsyBY72IW7c KaE7LeRGXpW9BNTQkLAYmE9wgJmvz67/+9Kl5OfEGpNKsgaDPc6szjLnyGhW6jht3FTUTEMID X/kj42BN3RY/hzSlfv73raCU2Xq0vCJs7YCWr6mYHwiX2jYchEN5NJfoStqIqAx+PVxTyqAW+ 5AJcLpb1KfXvWO8455Tl3pH9h4gTVhLpZBF22a28PG6WIZLG06/Bc8r4f+7hEx/d3Nsb+93ma QUIcMpyzg34VAK/EUMiXn3T8xZlYH1Yfx8URtQ== Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org The driver uses hardwire MMIO addresses instead of the data that is passed in device tree. Change it over to only hardcode the register offset values and allow compile-testing. Signed-off-by: Arnd Bergmann --- drivers/gpio/Kconfig | 8 +++++ drivers/gpio/Makefile | 2 +- drivers/gpio/gpio-lpc32xx.c | 63 ++++++++++++++++++++++++------------- 3 files changed, 50 insertions(+), 23 deletions(-) -- 2.20.0 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index bb13c266c329..ae86ee963eae 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -311,6 +311,14 @@ config GPIO_LPC18XX Select this option to enable GPIO driver for NXP LPC18XX/43XX devices. +config GPIO_LPC32XX + tristate "NXP LPC32XX GPIO support" + default ARCH_LPC32XX + depends on OF_GPIO && (ARCH_LPC32XX || COMPILE_TEST) + help + Select this option to enable GPIO driver for + NXP LPC32XX devices. + config GPIO_LYNXPOINT tristate "Intel Lynxpoint GPIO support" depends on ACPI && X86 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index a4e91175c708..87d659ae95eb 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -74,7 +74,7 @@ obj-$(CONFIG_GPIO_LP3943) += gpio-lp3943.o obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o -obj-$(CONFIG_ARCH_LPC32XX) += gpio-lpc32xx.o +obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o diff --git a/drivers/gpio/gpio-lpc32xx.c b/drivers/gpio/gpio-lpc32xx.c index 24885b3db3d5..548f7cb69386 100644 --- a/drivers/gpio/gpio-lpc32xx.c +++ b/drivers/gpio/gpio-lpc32xx.c @@ -16,8 +16,7 @@ #include #include -#include -#include +#define _GPREG(x) (x) #define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000) #define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004) @@ -72,12 +71,12 @@ #define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX) struct gpio_regs { - void __iomem *inp_state; - void __iomem *outp_state; - void __iomem *outp_set; - void __iomem *outp_clr; - void __iomem *dir_set; - void __iomem *dir_clr; + unsigned long inp_state; + unsigned long outp_state; + unsigned long outp_set; + unsigned long outp_clr; + unsigned long dir_set; + unsigned long dir_clr; }; /* @@ -167,14 +166,26 @@ struct lpc32xx_gpio_chip { struct gpio_regs *gpio_grp; }; +void __iomem *gpio_reg_base; + +static inline u32 gpreg_read(unsigned long offset) +{ + return __raw_readl(gpio_reg_base + offset); +} + +static inline void gpreg_write(u32 val, unsigned long offset) +{ + __raw_writel(val, gpio_reg_base + offset); +} + static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, unsigned pin, int input) { if (input) - __raw_writel(GPIO012_PIN_TO_BIT(pin), + gpreg_write(GPIO012_PIN_TO_BIT(pin), group->gpio_grp->dir_clr); else - __raw_writel(GPIO012_PIN_TO_BIT(pin), + gpreg_write(GPIO012_PIN_TO_BIT(pin), group->gpio_grp->dir_set); } @@ -184,19 +195,19 @@ static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group, u32 u = GPIO3_PIN_TO_BIT(pin); if (input) - __raw_writel(u, group->gpio_grp->dir_clr); + gpreg_write(u, group->gpio_grp->dir_clr); else - __raw_writel(u, group->gpio_grp->dir_set); + gpreg_write(u, group->gpio_grp->dir_set); } static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group, unsigned pin, int high) { if (high) - __raw_writel(GPIO012_PIN_TO_BIT(pin), + gpreg_write(GPIO012_PIN_TO_BIT(pin), group->gpio_grp->outp_set); else - __raw_writel(GPIO012_PIN_TO_BIT(pin), + gpreg_write(GPIO012_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); } @@ -206,31 +217,31 @@ static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group, u32 u = GPIO3_PIN_TO_BIT(pin); if (high) - __raw_writel(u, group->gpio_grp->outp_set); + gpreg_write(u, group->gpio_grp->outp_set); else - __raw_writel(u, group->gpio_grp->outp_clr); + gpreg_write(u, group->gpio_grp->outp_clr); } static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group, unsigned pin, int high) { if (high) - __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); + gpreg_write(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); else - __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); + gpreg_write(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); } static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group, unsigned pin) { - return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), + return GPIO012_PIN_IN_SEL(gpreg_read(group->gpio_grp->inp_state), pin); } static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, unsigned pin) { - int state = __raw_readl(group->gpio_grp->inp_state); + int state = gpreg_read(group->gpio_grp->inp_state); /* * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped @@ -242,13 +253,13 @@ static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group, unsigned pin) { - return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin); + return GPI3_PIN_IN_SEL(gpreg_read(group->gpio_grp->inp_state), pin); } static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group, unsigned pin) { - return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin); + return GPO3_PIN_IN_SEL(gpreg_read(group->gpio_grp->outp_state), pin); } /* @@ -498,6 +509,10 @@ static int lpc32xx_gpio_probe(struct platform_device *pdev) { int i; + gpio_reg_base = devm_platform_ioremap_resource(pdev, 0); + if (gpio_reg_base) + return -ENXIO; + for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) { if (pdev->dev.of_node) { lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate; @@ -527,3 +542,7 @@ static struct platform_driver lpc32xx_gpio_driver = { }; module_platform_driver(lpc32xx_gpio_driver); + +MODULE_AUTHOR("Kevin Wells "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("GPIO driver for LPC32xx SoC");