| Message ID | 20220311094515.3223023-2-vincent.whitchurch@axis.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/2] dt-bindings: serial: samsung: Add ARTPEC-8 UART | expand |
diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index 2940afb874b3..c2423144a4d6 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -20,6 +20,7 @@ properties: items: - enum: - apple,s5l-uart + - axis,artpec8-uart - samsung,s3c2410-uart - samsung,s3c2412-uart - samsung,s3c2440-uart @@ -110,6 +111,7 @@ allOf: contains: enum: - apple,s5l-uart + - axis,artpec8-uart - samsung,exynos4210-uart then: properties:
Add a compatible for the UART on the ARTPEC-8 SoC. This hardware block is closely related to the variants used on the Exynos chips. The register layout is identical to Exynos850 et al but the fifo size is different (64 bytes in each direction for all instances). Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> --- Notes: v2: - Expand commit message. - Define required clocks. Documentation/devicetree/bindings/serial/samsung_uart.yaml | 2 ++ 1 file changed, 2 insertions(+)