| Message ID | 20221201110237.7917-1-cniedermaier@dh-electronics.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [V3,1/4] dt-bindings: serial: rs485: Add GPIO controlling RX enable during TX | expand |
On Thu, 01 Dec 2022 12:02:34 +0100, Christoph Niedermaier wrote: > Add a binding for a generic definition of an output GPIO that sets the > state of rs485-rx-during-tx. The idea is that the hardware already controls > the option receiving during sending before it gets to the signal receiving > hardware. The standard RS485 is a half-duplex bus that in most cases is > driven by an UART controller. The advantage of using this GPIO is that it > is independent of the capabilities of the UART core and the UART driver. > On the hardware side the interface to the bus is controlled by a transceiver, > that has a pin called RE (RX Enable) or similar, which connects the bus to > the RX signal of the UART controller. The GPIO can switch between two states > to control the RE pin via an electrical circuit: > - Active: > The RE pin is always active. The UART RX see everything on the bus and > therefore also what happens with the TX signal on the bus. > - Inactive: > The RE pin is always active, but during sending on the bus the pin RE is > inactive. So basically the receiving during sending is suppressed. > > A possible circuit diagram could look like this: > ┌──────────────────┐ > │ RS485 │ > TX ───────────────┤D │ > │ Transceiver │ > RTS ────┬──────────┤DE │ > │ │ │ > │ ┌─────┐ │ │ > └─┤& │ │ │ > │ ├──┤!RE │ > !rx_during_tx_gpio ──────┤ │ │ │ > └─────┘ │ │ > │ │ > RX ───────────────┤R │ > │ │ > └──────────────────┘ > > Here the RTS pin of the UART core is used to control TX via the transceiver > pin DE (Drive Enable). RE and rx_during_tx_gpio are active low. > > Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> > --- > Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> > Cc: Alexander Dahl <ada@thorsis.com> > Cc: Marek Vasut <marex@denx.de> > Cc: kernel@dh-electronics.com > Cc: devicetree@vger.kernel.org > To: linux-serial@vger.kernel.org > To: linux-arm-kernel@lists.infradead.org > --- > V2: - Rework of the commit message > - Rework GPIO property comment > V3: - Rework the binding description > - Rework message title > - Rework of the commit message > --- > Documentation/devicetree/bindings/serial/rs485.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/serial/rs485.yaml b/Documentation/devicetree/bindings/serial/rs485.yaml index 90a1bab40f05..a973ab7d7e46 100644 --- a/Documentation/devicetree/bindings/serial/rs485.yaml +++ b/Documentation/devicetree/bindings/serial/rs485.yaml @@ -51,6 +51,12 @@ properties: description: GPIO pin to enable RS485 bus termination. maxItems: 1 + rs485-rx-during-tx-gpios: + description: Output GPIO pin that sets the state of rs485-rx-during-tx. This + signal can be used to control the RX part of an RS485 transceiver. Thereby + the active state enables RX during TX. + maxItems: 1 + additionalProperties: true ...
Add a binding for a generic definition of an output GPIO that sets the state of rs485-rx-during-tx. The idea is that the hardware already controls the option receiving during sending before it gets to the signal receiving hardware. The standard RS485 is a half-duplex bus that in most cases is driven by an UART controller. The advantage of using this GPIO is that it is independent of the capabilities of the UART core and the UART driver. On the hardware side the interface to the bus is controlled by a transceiver, that has a pin called RE (RX Enable) or similar, which connects the bus to the RX signal of the UART controller. The GPIO can switch between two states to control the RE pin via an electrical circuit: - Active: The RE pin is always active. The UART RX see everything on the bus and therefore also what happens with the TX signal on the bus. - Inactive: The RE pin is always active, but during sending on the bus the pin RE is inactive. So basically the receiving during sending is suppressed. A possible circuit diagram could look like this: ┌──────────────────┐ │ RS485 │ TX ───────────────┤D │ │ Transceiver │ RTS ────┬──────────┤DE │ │ │ │ │ ┌─────┐ │ │ └─┤& │ │ │ │ ├──┤!RE │ !rx_during_tx_gpio ──────┤ │ │ │ └─────┘ │ │ │ │ RX ───────────────┤R │ │ │ └──────────────────┘ Here the RTS pin of the UART core is used to control TX via the transceiver pin DE (Drive Enable). RE and rx_during_tx_gpio are active low. Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> --- Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Alexander Dahl <ada@thorsis.com> Cc: Marek Vasut <marex@denx.de> Cc: kernel@dh-electronics.com Cc: devicetree@vger.kernel.org To: linux-serial@vger.kernel.org To: linux-arm-kernel@lists.infradead.org --- V2: - Rework of the commit message - Rework GPIO property comment V3: - Rework the binding description - Rework message title - Rework of the commit message --- Documentation/devicetree/bindings/serial/rs485.yaml | 6 ++++++ 1 file changed, 6 insertions(+)