Message ID | 20250515141828.43444-2-thierry.bultel.yh@bp.renesas.com |
---|---|
State | New |
Headers | show |
Series | [v9,01/10] dt-bindings: serial: Added secondary clock for RZ/T2H RSCI | expand |
Hi Thierry, On Thu, 15 May 2025 at 16:18, Thierry Bultel <thierry.bultel.yh@bp.renesas.com> wrote: > At boot, the default clock is the PCLKM core clock (synchronous > clock, which is enabled by the bootloader). > For different baudrates, the asynchronous clock input must be used. > Clock selection is made by an internal register of RCSI. > > Also remove the unneeded serial0 alias from the dts example. > > Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> > --- > Changes v8->v9: > - typo in description > - named clocks 'operational' and 'bus', and added optional 'sck' clock > - uses value of 2nd core clock in example to break the dependency on cpg patch Thanks for the update! > --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml > +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml > @@ -35,10 +35,17 @@ properties: > - const: tei > > clocks: > - maxItems: 1 > + minItems: 2 > + maxItems: 3 > > clock-names: > - const: fck # UART functional clock > + minItems: 2 > + maxItems: 3 I think you can drop the maxItems. > + items: > + enum: > + - operation > + - bus > + - sck # optional external clock input The addition of this (third) clock is not mentioned in the patch description. > > power-domains: > maxItems: 1 > @@ -58,11 +65,7 @@ unevaluatedProperties: false > examples: > - | > #include <dt-bindings/interrupt-controller/arm-gic.h> > - #include <dt-bindings/clock/renesas-cpg-mssr.h> > - > - aliases { > - serial0 = &sci0; > - }; > + #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h> Now you no longer use any definitions from this header file, please keep on using <dt-bindings/clock/renesas-cpg-mssr.h> instead, to relax the dependency on [PATCH v9 02/10]. > > sci0: serial@80005000 { > compatible = "renesas,r9a09g077-rsci"; > @@ -72,7 +75,7 @@ examples: > <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>, > <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "eri", "rxi", "txi", "tei"; > - clocks = <&cpg CPG_MOD 108>; > - clock-names = "fck"; > + clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE 13>; > + clock-names = "operation", "bus"; > power-domains = <&cpg>; > }; The rest LGTM. Gr{oetje,eeting}s, Geert
diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml index ea879db5f485..e966d2b5f16d 100644 --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml @@ -35,10 +35,17 @@ properties: - const: tei clocks: - maxItems: 1 + minItems: 2 + maxItems: 3 clock-names: - const: fck # UART functional clock + minItems: 2 + maxItems: 3 + items: + enum: + - operation + - bus + - sck # optional external clock input power-domains: maxItems: 1 @@ -58,11 +65,7 @@ unevaluatedProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/clock/renesas-cpg-mssr.h> - - aliases { - serial0 = &sci0; - }; + #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h> sci0: serial@80005000 { compatible = "renesas,r9a09g077-rsci"; @@ -72,7 +75,7 @@ examples: <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "tei"; - clocks = <&cpg CPG_MOD 108>; - clock-names = "fck"; + clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE 13>; + clock-names = "operation", "bus"; power-domains = <&cpg>; };
At boot, the default clock is the PCLKM core clock (synchronous clock, which is enabled by the bootloader). For different baudrates, the asynchronous clock input must be used. Clock selection is made by an internal register of RCSI. Also remove the unneeded serial0 alias from the dts example. Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> --- Changes v8->v9: - typo in description - named clocks 'operational' and 'bus', and added optional 'sck' clock - uses value of 2nd core clock in example to break the dependency on cpg patch --- .../bindings/serial/renesas,rsci.yaml | 21 +++++++++++-------- 1 file changed, 12 insertions(+), 9 deletions(-)