From patchwork Thu Jun 11 03:25:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Yilun X-Patchwork-Id: 214438 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7137AC433E1 for ; Thu, 11 Jun 2020 03:28:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 514A3207C3 for ; Thu, 11 Jun 2020 03:28:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726312AbgFKD2u (ORCPT ); Wed, 10 Jun 2020 23:28:50 -0400 Received: from mga18.intel.com ([134.134.136.126]:28223 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726290AbgFKD2u (ORCPT ); Wed, 10 Jun 2020 23:28:50 -0400 IronPort-SDR: yUiP/E+kCWGaPqHB8vxDgdGF8JXwjmTuTwSpLFnPcR0F8HrcY/eVdpPH4NRWqPzpN+OX4CHl7J P3QKIjqnSE4Q== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2020 20:28:49 -0700 IronPort-SDR: LalyfZGMnEkL6uRGWaE29LKoLCyRxmdx6MmY4lyUAxdKxrOhYGrv49NWuo5DTUQflDPIHtUcBl w3s7aA5vVCXg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,498,1583222400"; d="scan'208";a="260587328" Received: from yilunxu-optiplex-7050.sh.intel.com ([10.239.159.141]) by fmsmga008.fm.intel.com with ESMTP; 10 Jun 2020 20:28:47 -0700 From: Xu Yilun To: broonie@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: trix@redhat.com, yilun.xu@intel.com, hao.wu@intel.com, matthew.gerlach@linux.intel.com, russell.h.weight@intel.com Subject: [PATCH 0/6] Add more configuration and regmap support for spi-altera Date: Thu, 11 Jun 2020 11:25:05 +0800 Message-Id: <1591845911-10197-1-git-send-email-yilun.xu@intel.com> X-Mailer: git-send-email 2.7.4 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This patchset adds platform_data for spi-altera, to enable more IP configurations, and creating specific spi client devices. It also adds regmap support, to enable the indirect access to this IP. We have a PCIE based FPGA platform which integrates this IP to communicate with a BMC chip (Intel MAX10) over SPI. The IP is configured as 32bit data width. There is also an indirect access interface in FPGA for host to access the registers of this IP. This patchset enables this use case. Matthew Gerlach (1): spi: altera: fix size mismatch on 64 bit processors Xu Yilun (5): spi: altera: add 32bit data width transfer support. spi: altera: add SPI core parameters support via platform data. spi: altera: add platform data for slave information. spi: altera: use regmap instead of direct mmio register access spi: altera: move driver name string to header file drivers/spi/Kconfig | 1 + drivers/spi/spi-altera.c | 161 +++++++++++++++++++++++++++++++++++++-------- include/linux/spi/altera.h | 37 +++++++++++ 3 files changed, 171 insertions(+), 28 deletions(-) create mode 100644 include/linux/spi/altera.h